Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience in Design Verification (DV).
Experience in developing and deploying state of the art verification methodologies.
Experience in any one of the hardware description languages (HDL) (e.g. Verilog/SystemVerilog).
Experience with Python for scripting, automation, and data analysis in a verification context.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience with AI/ML frameworks and tools such as TensorFlow, PyTorch, or ONNX, particularly in how they relate to hardware implementation and verification.
Understanding of modern verification methodologies (e.g., UVM, Specman, Formal Verification).
Understanding of AI/ML fundamentals, including various neural network architectures (CNNs, RNNs, Transformers), ML algorithms, and concepts like training, inference, quantization, and activation functions.