Master’s degree or foreign equivalent in Electrical Engineering, Computer Engineering, or related field and 2 years of experience in the job offered or related occupation.
Experience and/or education with the following skills:
Perl to automate and execute design flows
ATPG, Test compression, Tessent to perform Scan pattern generation and fault coverage
Scan diagnosis to analyze silicon failures from ATE and improve yield and manufacturing process
Verilog, System Verilog for design and verification