Job Description:
(ii) Continuous advancement of holistic physical verification methodology and solution.
(iii) Develop and implement quality assurance workflow in physical verification runset development.
(iv) Develop automation supporting runset development.
Qualifications:Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications:
- Candidate must possess a BS degree with 5+ years of experience or MS degree with 4+ years of experience or PhD degree with 3+ years of experience in Electronics Engineering, Electrical Engineering and Computer Engineering or related field.
3+ years of experience in the following:
- DRC/LVS/Antenna/Fill runset development in Calibre-SVRF, ICV-PXL, or Pegasus language.
- Develop and implement physical verification runset QA workflow, including testcases development.
- Scripting in Python, PERL or TCL.
Preferred Qualifications:
3+ years of experience in the following:
- PDK development.
- IC physical design, layout, and verification flows.
- Experienced in PERC verification development.
- Knowledge and understanding in advanced process nodes layout design rules implementation.
- C++ based EDA tool/software development.
- Knowledge of IC manufacturing process flows.
- Exposure to CAD/CAE environments involving circuit simulation, physical verification, parasitic extraction, P2P resistance/current density analysis and net listing tools.
- Software development practices such as Agile and Test Driven Development.
Experienced HireShift 1 (Malaysia)Malaysia, Penang