Client Soc Power Modeling Optimization jobs in Israel
Nvidia Physical Design Power Optimization Engineer Israel, North District
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- Israel, Yokneam
- Israel, Tel Aviv
- time type
- Full time
- posted on
- Posted Today
- job requisition id
What you will be doing:
Power Optimization of Physical design, of blocks/top-level/fc under challenging constraints.
Optimization involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise fixes.
Power estimation and power modeling.
What we need to see:
B.SC./ M.SC. or equivalent experience in Electrical Engineering/Computer Engineering.
2+ years of experience in physical design and/or BE power optimization aspects.
Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).
Knowledge in physical design flows and methodologies (PNR, STA, physical verification) is an advantage.
FE design experience is an advantage.
Excellent problem-solving, partnership, and interpersonal skills.
These jobs might be a good fit
Google Software Engineer CPU Performance Modeling Google Cloud Israel, Tel Aviv District, Tel Aviv-Yafo
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- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
- 2 years of experience with software development in C++ programming language or 1 year of experience with an advanced degree.
Preferred qualifications:
- Master’s degree or PhD in Engineering, Computer Science, or a related technical field.
- 2 years of experience with data structures or algorithms.
- Experience in modern CPU/Machine Learning (ML) architecture and micro-architecture.
- Ability to learn coding languages.
- Excellent object-oriented database design and SQL skills.
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Google Power Signal Integrity Engineer Israel, Haifa District, Haifa
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- Bachelor's degree in Mechanical, Electrical Engineering, Material Science, or equivalent practical experience.
- 5 years of experience in signal or power integrity or hardware design.
Preferred qualifications:
- Experience with industry-standard Electronic Design Automation (EDA) tools for simulation and layout (e.g., Cadence Sigrity/Allegro, Ansys HFSS/PowerDC/Q3D, Keysight ADS, Synopsys HSPICE).
- Proficiency in scripting languages such as Python, Perl, or Tcl for flow automation and data analysis.
- Familiarity with high-speed testing equipment like VNAs, TDRs, and oscilloscopes for measurement and validation.
- Knowledge of circuit analysis, electromagnetics, and transmission line theory.
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Google SoC DFT Engineer Google Cloud Israel, Tel Aviv District, Tel Aviv-Yafo
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- Bachelor's degree in Electrical Engineering, a related field, or equivalent practical experience.
- 3 years of experience with Design For Test (DFT) methodologies, DFT verification, and industry-standard DFT tools.
- Experience with ASIC DFT synthesis, simulation, and verification flow.
- Experience in DFT specification, definition, architecture, and insertion.
Preferred qualifications:
- Master's degree in Electrical Engineering.
- Experience working with ATE engineers (e.g., silicon bring-up, patterns generation, debug, validation on automatic test equipment, debug of silicon issues).
- Experience in IP integration (e.g., memories, test controllers, Test Access Point (TAP), and Memory Built-In Self Test (MBIST)).
- Experience in SoC cycles, silicon bringup, and silicon debug activities.
- Experience in fault modeling.
These jobs might be a good fit
Google SOC Design Verification Engineer Google Cloud Israel, Tel Aviv District, Tel Aviv-Yafo
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- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 4 years of experience with creating and using verification components and environments in standard verification methodology.
- Experience verifying digital systems using standard IP components/interconnects (microprocessor cores, hierarchical memory subsystems).
- Experience verifying digital logic at RTL level using SystemVerilog or Specman/E for FPGAs or ASICs.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with verification techniques, and the full verification life-cycle.
- Experience with performance verification of ASICs and ASIC components.
- Experience with ASIC standard interfaces and memory system architecture.
These jobs might be a good fit
Amazon Junior Signal Power integrity Engineer Israel, Haifa District, Haifa
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Key job responsibilities
As a SIP engineer, you will be involved in:
• Work on advanced high-speed interfaces such as PCIe, DDR and Ethernet.
• End-to-end solution of high-speed interfaces; from floor-planning at the DIE level, through Package and PCB routing, addressing both robust SI/PI considerations as well as optimizing layout routing.
• Signal and power integrity modeling and simulation of high-speed interconnects using advanced SI/PI simulation tools.
• Hands-on lab work involving oscilloscopes, spectrum analyzers, and other RF/mixed-signal measurement equipment, for advanced electrical characterization.You will undergo a comprehensive training program, providing you with the essential knowledge and skills required to succeed in this field. The work is multidisciplinary, bridging physical design, electromagnetic theory, and practical engineering challenges.
Preferred Qualifications
- Communication, Electromagnetics, Signal processing, Microelectronics.
- Previous experience with lab equipment (e.g oscilloscope, spectrum analyzer).
- Familiarity with simulation/extraction tools (e.g. HFSS, Sigrity, HSpice).
These jobs might be a good fit
Google Senior SoC Design Verification Engineer Google Cloud Israel, Haifa District, Haifa
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- Bachelor's degree in Electrical Engineering or equivalent practical experience.
- 8 years of experience with creating and using verification components and environments in standard verification methodology.
- Experience verifying digital logic at RTL level using SystemVerilog or Specman/E for FPGAs or ASICs.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering.
- Experience with verification techniques, and the full verification life cycle.
- Experience with performance verification of ASICs and ASIC components.
- Experience with Application-Specific Integrated Circuit (ASIC) standard interfaces and memory system architecture.
- Experience in four or more System on a chip (SOC) cycles.
These jobs might be a good fit
Share
- Israel, Yokneam
- Israel, Tel Aviv
- time type
- Full time
- posted on
- Posted Today
- job requisition id
What you will be doing:
Power Optimization of Physical design, of blocks/top-level/fc under challenging constraints.
Optimization involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise fixes.
Power estimation and power modeling.
What we need to see:
B.SC./ M.SC. or equivalent experience in Electrical Engineering/Computer Engineering.
2+ years of experience in physical design and/or BE power optimization aspects.
Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).
Knowledge in physical design flows and methodologies (PNR, STA, physical verification) is an advantage.
FE design experience is an advantage.
Excellent problem-solving, partnership, and interpersonal skills.
These jobs might be a good fit
