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What you will be doing:
Power Optimization of Physical design, of blocks/top-level/fc under challenging constraints.
Optimization involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise fixes.
Power estimation and power modeling.
What we need to see:
B.SC./ M.SC. or equivalent experience in Electrical Engineering/Computer Engineering.
2+ years of experience in physical design and/or BE power optimization aspects.
Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).
Knowledge in physical design flows and methodologies (PNR, STA, physical verification) is an advantage.
FE design experience is an advantage.
Excellent problem-solving, partnership, and interpersonal skills.
These jobs might be a good fit

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We are looking for a talented and experienced Product Designer to help shape the future of our B2B platform. In this role, you’ll join the Measurement group, working as part of a cross-functional squad alongside product managers, engineers, analysts, and other designers.
You’ll take full ownership of the design process — from uncovering user needs and surfacing hidden opportunities to ideating, prototyping, and designing intuitive, visually polished solutions. You’ll also play a key role in building feedback loops that help the product evolve and deliver meaningful impact.
What you’ll do
What you have
Bonus Points
Oren Kaniel, CEO

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We expect you to be:
Experience:

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You will be part of the Post Silicon SW Tool & Automation team in NVIDIA, a team responsible for the infrastructure, GUI tools, and all SW-related applications of the high-speed communication products, and be working with RND teams to ensure outstanding products and superb automated tools. You’ll work at the HW/SW interface, developing critical tools and automation that support silicon bring-up, SerDes validation, and emerging system platforms.
What you will be doing
Develop python based software and infrastructure to control NVIDIA hardware, with a focus on mixed-signal IP and SerDes functionality, and to enable silicon bring-up, validation, and regression testing through automation tools.
Collaborate closely with cross-functional teams (RTL, Architecture, Algorithms, Post-Silicon) to align the software environment with evolving requirements.
Debug and troubleshoot at the HW/SW boundary using waveforms, logs, and lab measurements for robust system validation.
What we need to see
B.Sc in Electrical Engineering.
5+ years of relevant industry experience (SerDes, digital/analog architecture, hardware/software integration).
Python programming and debugging skills.
Experience building software that interfaces with device drivers and exposes hardware functionality.
Deep understanding of digital and analog system architectures.
Ways to stand out from the crowd
Deep understanding of SerDes architectures and link bring-up processes.
Knowledge of communication systems(transmitters/receivers),optics modulators.
Hands-on experience with post-silicon hardware bring-up and lab instrumentation (oscilloscopes, spectrum analyzers, etc.).
Proficiency in object-oriented Python development and design patterns.
Experience using version control tools (e.g., GIT).

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As a Senior Product Designer for Elementor Editor, you will join the Editor product group, helping them to drive their vision and build new and exciting experiences.
You will work cross-functionally with product managers, engineers, content designers, product marketing, marketing and support operations, to deliver exceptional product flows, features, visual concepts and more.
Nice to have:

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1. Submit your application
2. Complete your online assessment
3. First interview will be completed by 2-weeks after completing online assessment
4. Final interviews will be completed by 3-weeks after completing first interview depending on slot availability.1. 応募書類の提出
2. オンラインアセスメント
3. 一次面接
4. 最終面接
(応募から最終面接まで1‐2か月を想定しています)
- Bachelor’s Degree in Computer Science or related field
- Available to join in 2025
- Within 2 year after graduating university when application is complete
- Computer Science fundamentals in object-oriented design
- Computer Science fundamentals in data structures Computer Science fundamentals in algorithm design, problem solving, and complexity analysis
- Proficiency with the tools of the trade, including a variety of modern programming languages (Java, C/C++, Objective C, Python, JavaScript, etc.) and open-source technologies (Linux, Spring, JQuery, etc.)
- Business Level English Communication Skills

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What you'll be doing:
Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.
Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
Taking part in flows development.
What we need to see:
B.SC./ M.SC. in Electrical Engineering/Computer Engineering or equivalent work experience.
5+ years of experience in Physical Design.
Proven experience in RTL2GDS flows and methodologies.
Knowledge in physical design flows and methodologies (PNR, STA, physical verification).
Deep understanding of all aspects of Physical construction and Integration.
Strong background of Physical Design Verification methodology LVS/DRC.
Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc).
Great teammate.

Share
What you will be doing:
Power Optimization of Physical design, of blocks/top-level/fc under challenging constraints.
Optimization involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise fixes.
Power estimation and power modeling.
What we need to see:
B.SC./ M.SC. or equivalent experience in Electrical Engineering/Computer Engineering.
2+ years of experience in physical design and/or BE power optimization aspects.
Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).
Knowledge in physical design flows and methodologies (PNR, STA, physical verification) is an advantage.
FE design experience is an advantage.
Excellent problem-solving, partnership, and interpersonal skills.
These jobs might be a good fit