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Senior Test Timing Engineer jobs at Nvidia
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764 jobs found
22.06.2024
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Nvidia Senior Test Timing Engineer United States, California
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Drive DFT/Test timing for innovative GPUs, CPUs, and SoCs at cluster level and/or full chip level. Work on all aspects of DFT/Test timing such as timing constraints, timing analysis, timing...
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22.06.2024
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Nvidia Senior Timing Methodology Engineer United States, California
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Develop and validate flows for PT-STA regression, analysis, QOR metrics for high-speed designs. The focus is on CAD flow development and analysis which is the primary task. Developflows/recommendations. Collaborate with...
23.06.2024
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Nvidia Senior ASIC Engineer Timing United States, California
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You will drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, with a focus on netlist-related aspects such as equivalence...
23.06.2024
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Nvidia Senior ASIC Timing Engineer United States, California
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You will be responsible for all aspects of timing including, timing analysis and closure, timing environment, setting up constraints and defining the timing methodology for the next generation of designs....
23.06.2024
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Nvidia Senior ASIC Timing Engineer United States, California
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Develop and execute timing closure plans for NVIDIA's next generation of CPU, GPU or SOC designs. Owning STA of large subsystems and full chip designs or at block-level with additional...
23.06.2024
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Nvidia Senior ASIC Timing Engineer United States, Texas
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You will drive physical design and timing of high-frequency and low-power DPUs and SoCs at block level, cluster level, and/or full chip level. Analyze and optimize design constraints and synthesis...
30.07.2024
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Nvidia Senior ASIC Engineer Timing United States, California
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Description:Full job details
You will drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, with a focus on netlist-related aspects such as equivalence...
Description:Full job details
Drive DFT/Test timing for innovative GPUs, CPUs, and SoCs at cluster level and/or full chip level. Work on all aspects of DFT/Test timing such as timing constraints, timing analysis, timing...
These jobs might be a good fit
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