Senior Software Architect - Deep Learning Hpc Communications jobs at Nvidia in Taiwan, Hsinchu

What You'll be Doing:

• Work on architecture and design of our state-of-the-art high speed coherent interconnects (NVLINK-C2C) for our mobile SoCs and GPUs.

• Collaborate with architects, external partners, software engineers, and circuit designers to deliver a class leading high speed coherent interconnect.

• Optimize design based on features, requirements, and system limitations”

What We Need to See:

• BS or equivalent experience in Electrical Engineering or Computer Engineer or related degree required.

• 5+ years or relevant design experience and knowledge in architecture, RTL design, performance analysis and power optimization.

• Knowledge of industry standard interconnect protocols like PCIE, CXL, AXI, CHI will be useful.

• Strong working knowledge of Verilog or System Verilog.

• Good communication skills and interpersonal skills are required.

Ways to stand out from the crowd:

• Master or PhD degree will be a preferred.

• A history of mentoring junior engineers and interns a huge plus.

What you'll be doing:

• Leading the development of groundbreaking microelectronics packaging for NVIDIA Networking Business Unit's future products

• Collaborating with world-leading vendors to develop highly ambitious packaging solutions

• Thriving in a dynamic and challenging environment

• Joining and leading task forces to investigate and support production excursions, failure analysis, and reliability issues

What we need to see:

• BSc or equivalent experience in Mechanical Engineering / Materials Engineering / Physics or similar

• 10+ years of experience ,at least 5 years of experience with complex ASIC package development and manufacturing

• Experience co-working with subcontractors and vendors

• Vision and focus for projects and team

• Curious and creative problem solver as well as organized and multi-tasker

• Team oriented, able to move and motivate peers. Strong interpersonal skills (verbal and written)

• High awareness of quality, manufacturability and project schedule

Ways to stand out of the crowd:

• Hands-on FEA mechanical simulation experience

• Team / Group / Project management - advantage

• Experience with manufacturing environment and manufacturing statistics tools (for example – JMP)

• Background in semiconductor manufacturing processes

What you’ll be doing:

• Be involved in some design work for the IPs and features owned by System-ASIC team

• Brainstorm with IP design owners to figure out suffering points or discuss infra-related improvement ideas. Settle down the specific requirement and choose the suitable methodology to develop infrastructure flow/tool

• Responsible for Reset methodology work, include: utilize in-house or industry commercial tool and flow to guarantee reset design quality, develop new tool or flow to improve reset design quality and efficiency

What we need to see:

• MS in EE/CE/CS

• 2+ years of design or design methodology experience

• Strong coding skill for Python, Perl, TCL, JavaScript etc.

• Understand ASIC design/verification flow and have experience forCDC/RDC/Synthesis/Timingclosure

• Fluent English (both written and spoken) and excellent communication skills to interface with many groups and build consensus

Ways to stand out from the crowd:

• Good team work spirit, easy to cooperate with team members

• Has Web system, Database knowledge is a plus

• Knowledge on deep-learning experience is a plus

What you’ll be doing:

• A senior role in physical design for NVIDIA GPU and Mobile chips.

• Participate in various aspects of physical design, including full chip floorplanning, power/clock distribution, timing optimization, place & route, timing closure, power/signal integrity analysis, and physical verification. Troubleshoot a wide variety of design and flow complicated issues, and apply proactive intervention.

• Collaborate with RTL, DFT and Circuit designers to ensure high quality of design implementation.

What we need to see:

• BS in Engineering or Science or equivalent experience

• Power user of EDA tools from Synopsys(ICC2/DC/PT/STAR-RC),Cadence (EDI/Innovus/Voltus) or Ansys (Redhawk)

• Experience in Clock/Power Distribution, P&R, Timing closure, RC Extraction, and verification on advanced technology nodes

• 2+ years of experience in above areas

Ways to stand out from the crowd:

• MS in Engineering or Science

• Knowledge in FinFET technology, circuit design, and package design

• Experience in physical verification tools from Synopsys (ICV) or Mentor (Calibre)

• Proficiency in Perl, Python, TCL and Makefile scripts

What you’ll be doing:

• As a Clocks team member, you will need to run and enhance some in-house flows to guarantee the good quality of clocks RTL and netlist, drive the issues to close.

• You need collaborate with frontend team to make sure the clock structure follows some predefined rules.

• And work with backend team to make sure the clock is distributed/routed correctly. We have some special check for transition/skew, etc.

• You will use Perl/Python to improve the productivity.

What we need to see:

• BS or (MS preferred) in EE with 4+ years of meaningful work experience.

• Ability to thrive in a dynamically changing environment.

• Strong coding skills in Perl or Python or other industry-standard scripting languages.

• Deep understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects is a plus.

• Good understanding of backend flows and requirements is a plus.

• DFT knowledge is a plus.

• Experience in implementing on-chip clocking networks is desirable.

Ways to stand out from the crowd:

• Excellent analytical and problem-solving skills.

• Fluent English (both written and spoken) and excellent communication skills.

• Good team work spirit, easy to cooperate with team members.

What you'll be doing:

• Develop software for inhouse DFT use.

• Connect with users to spec out software behavior.

• Collaborate with programming experts to design algorithms, program architecture, and implementation.

• Improve infrastructure to verify the correctness of the software.

What we need to see:

• MS in Computer Science or Electrical Engineering

• Strong C++ Programming skills

• Knowledge on new C++ standards (C++11/14/17/20/23)

• Strong interpersonal skills and ability & desire to innovate

Ways to stand out from the crowd:

• Modern software testing framework knowledge. (e.g. gtest, TDD/BDD, etc.)

• Tcl/Python and other scripting languages

• Web services development experience is a plus

• IC design flow knowledge and EDA software experience is a plus

• AI related knowledge is a plus

What you’ll be doing:

• Your responsibilities include defining the chip pad ring, substrate interconnect scheme, and lead the package layout design process.

• We collaborate with large teams consisting of Circuit, Signal Integrity, RTL, Place and Route, substrate layout and system design Engineers and Managers.

• Work to define a chip floor plan, pad ring, substrate, and ball out implementing a robust world-class electrical package!

• Communicate effectively with various teams throughout the company

What we need to see:

• BSEE or equivalent experience.

• Minimum of 5+ years in board/system design. Experience with package design is preferred.

• Good understanding of transmission line theory, power delivery and signal integrity is desired.

• Strong programming and scripting skills in Perl, Python, Tcl desired, Cadence Skill and EXCEL familiarity are helpful.

• Enthusiastic and able to work with a minimum of supervision.

• You seek to solve complex technical problems.