Senior Physical Design Engineer jobs at Nvidia in Taiwan, Hsinchu

What you'll be doing:

• Verify the design and implementation of the industry's leading GPU

• Responsible for verification of the Mixed Signal CMOS circuit design, architecture, golden models using advanced verification methodologies

• You are expected to understand complex mixed-signal CMOS circuits design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.

• Work closely with Multi-functional teams, circuit and logic design, verification, test engineering to accomplish tasks.

What we need to see:

• Pursuing MS/PhD in EE with domain study in analog circuit design / mixed signal circuit design.

• Experience with design and verification tools (Cadence's IC design environment, analog circuit simulation tools like HSpice, Finesim, XA)

• Experience in crafting test bench environments for component and top level circuit verification

• Expertise in System Verilog or similar HVLand strong debugging and analytical skills

• Perl and C/C++ programming language experience desirable

• Strong communication skills and ability & desire to work as a great teammate are huge plus.

What you'll be doing:

• Mixed-Signal/Analog circuit design for High-Speed Memory I/O Interfaces

• Develop and implement high speed interfaces and analog circuits using the latest CMOS FinFET processes

• Help define circuit requirements and complete design from schematic, layout, and verification to characterization

• Optimize design to meet the specifications for system performance.

What we need to see:

• MS in Electrical Engineering, PhD is preferred.

• TX/RX related design experience or is fairly familiar with high-speed SerDes/analog circuit design concepts

• CMOS Analog / Mixed Signal Circuit Design Experience in deep sub-micron process (especially in FINFET)

• Strong background of Cadence custom design tools, various circuit simulators like Hspice, XA, FineSim, Spectre

• Experience in crafting test bench environments for component and top level circuit verification

• Knowledge of Verilog, Verilog-A, Matlab, or similar tools for behavioral modeling of analog and digital circuits is a plus

• Strong debugging and analytical skills

• Strong interpersonal skills and ability & desire to work as a good teammate

We are looking for a Digital Circuit Design Intern. As a member of our Mixed-Signal high-speed I/O SerDes group, you'll be working on NVDIA's latest ground breaking technology that enables and accelerates gaming, artificial intelligence, deep learning, and autonomous driving. Your design will be consumed by standard as well as industry-leading proprietary high-speed protocols, and will serve as one of the key IPs in many complex SoC. You'll work closely with analog designers and system architects to independently come up with micro-architecture specification and refine adaptation algorithms. You'll then implement the RTL in SystemVerilog, define test cases that will deeply verify the design and carry out test creations. Next is to define and build constraints for synthesis and drive for timing closure. In addition to RTL design, you'll need to understand the analog schematics and write SystemVerilog models that collects the functionality of those circuits in the most precise way.

What you'll be doing:

• Be actively involve in developing mixed-signal chips .

• Plan the specification, evaluate the PPA of algorithms, design the digital circuits such as filters and analog calibration circuits

• Verify the analog and digital design using direct test and random test

• Perform the frond-end design flows(Lint/CDC/Synthesis/DFT/LEC/STA)and co-work with back-end team to chip tape-out

• Help in silicon bring-up and fine-tune performance

What we need to see:

• Pursuing Master / PhD in Electrical Engineering.

• Solid understanding or experiencein high-speed SerDes I/O digital design, knowledge at protocol level (Ethernet, PCIE) preferred.

• Have a deep understanding of Verilog or SystemVerilog, logic design and circuit modeling in RTL for mixed-signal blocks; Experience with industry standard verification methodologies, such as UVM.

• Knowledge with custom digital circuit design and adaptation algorithms, such as FFE, DFE, CTLE, CDR, and offset cancellation.

• Familiar with static timing tools and formal verification tools.

• Have a strong background in Perl and Python scripting; If you have a background in computer architecture and deep learning, this is a plus.

In this position, you will get the opportunity to face the challenge in building the complex GPU and Tegra chips and have chances to use cutting edge technology to solve those challenges. You will also have chances to interact directly with unit-level ASIC, Physical Design, CAD, Package Design, Software, DFT and other teams.

What you'll be doing:

• Define and develop system-level methodologies and tools to build SOCs in an efficient and scalable manner

• Identify inefficiencies and improvement opportunities in the front-end chip implementation process and propose ideas to tackle them

• Using AI to solve SOC Design related challenges

• Padring related methodology development

What we need to see:

• MS in Computer or Electrical Engineering or equivalent experience

• 3+ years of proven experience in chip design, specializing in SOC integration and methodology

• Excellent analytical and problem-solving skills

• Experienced in HW design, including: RTL design (Verilog), System-On-Chip design/integration flow, and design automation

• Has dependency management experience in a project, has AI development experience, has database concept

• Experienced script skills: Perl, Python, or other industry-standard scripting languages.

• Great communication and teamwork skills to interact within the team and across functional teams to build consensus

What you will be doing:

• Support inventory control team for Chip, Boards and Data Center business, which including the areas of inventory transactions, reconciliation, aging inventory management, lot size optimizations, shipment arrangement with subcons, system user acceptance testing, and all IC tasks assigned.

• Secure components required for production through material planning (include Assy raw material and substrate raw material). To assist generating purchase requisitions and purchase orders

• Maintain quotation in SAP system (OSAT).; To generate the blanket PO to support the subcons business and operation. To execute the scrap audit in subcons. To execute the factory physical audit.

• Understand the critical role of the new product introduction planning team in executing the time-to-market plan of all the new products.

• Collaborate with team members and business partners from different geographical locations. To apply your creativity and give feedback to the team members on ways to improve the business flows and work efficiency.

What we need to see:

• Degree in Industrial Engineering, Industrial Engineering Management or Business Administration.

• Good communication, problem-solving, teamwork, interpersonal, and quantitative skills.

• Proficiency in business software applications such as Microsoft Office (Excel, PowerPoint, Outlook).

• Language: Fluent English skills on reading, writing, speaking, and listening.

• Personality: highly organized, detailed orientated, a self-starter with a strong sense of ownership.

Ways to stand out from the crowd:

• Demonstrating consistently the desire and ability to absorb knowledge on real world operational problems that hinder NVIDIA's ability to hit production goals.

• Working with internal and external team members with strong interpersonal skills to establish action plans that can improve the overall performance of the company.

What You'll be Doing:

• Work on architecture and design of our state-of-the-art high speed coherent interconnects (NVLINK-C2C) for our mobile SoCs and GPUs.

• Collaborate with architects, external partners, software engineers, and circuit designers to deliver a class leading high speed coherent interconnect.

• Optimize design based on features, requirements, and system limitations”

What We Need to See:

• BS or equivalent experience in Electrical Engineering or Computer Engineer or related degree required.

• 5+ years or relevant design experience and knowledge in architecture, RTL design, performance analysis and power optimization.

• Knowledge of industry standard interconnect protocols like PCIE, CXL, AXI, CHI will be useful.

• Strong working knowledge of Verilog or System Verilog.

• Good communication skills and interpersonal skills are required.

Ways to stand out from the crowd:

• Master or PhD degree will be a preferred.

• A history of mentoring junior engineers and interns a huge plus.

What you'll be doing:

• Leading the development of groundbreaking microelectronics packaging for NVIDIA Networking Business Unit's future products

• Collaborating with world-leading vendors to develop highly ambitious packaging solutions

• Thriving in a dynamic and challenging environment

• Joining and leading task forces to investigate and support production excursions, failure analysis, and reliability issues

What we need to see:

• BSc or equivalent experience in Mechanical Engineering / Materials Engineering / Physics or similar

• 10+ years of experience ,at least 5 years of experience with complex ASIC package development and manufacturing

• Experience co-working with subcontractors and vendors

• Vision and focus for projects and team

• Curious and creative problem solver as well as organized and multi-tasker

• Team oriented, able to move and motivate peers. Strong interpersonal skills (verbal and written)

• High awareness of quality, manufacturability and project schedule

Ways to stand out of the crowd:

• Hands-on FEA mechanical simulation experience

• Team / Group / Project management - advantage

• Experience with manufacturing environment and manufacturing statistics tools (for example – JMP)

• Background in semiconductor manufacturing processes