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Senior Asic Physical Design Engineer jobs at Nvidia in Taiwan, Hsinchu
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Taiwan
Hsinchu
33 jobs found
23.06.2024
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Nvidia Senior ASIC Physical Design Engineer Taiwan, Taiwan Province, Hsinchu
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STA for hierarchical design. Constraints creation and validation, timing budget. Timing closure for both partition and full chip level. Special timing closure, such as io, test, clock etc. Synthesis, Netlist...
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22.06.2024
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Nvidia Physical Design Engineer Taiwan, Taiwan Province, Hsinchu
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A senior role in physical design for NVIDIA GPU and Mobile chips. Participate in various aspects of physical design, including full chip floorplanning, power/clock distribution, timing optimization, place & route,...
22.06.2024
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Nvidia Physical Design Engineer Taiwan, Taiwan Province, Hsinchu
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A senior role in physical design for NVIDIA GPU and Mobile chips. Participate in various aspects of physical design, including full chip floorplanning, power/clock distribution, timing optimization, place & route,...
24.06.2024
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Nvidia Physical Design Engineer RDSS Intern Taiwan, Taiwan Province, Hsinchu
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Responsible for all aspects of physical design (Netlist to GDSII & Flow development) of all chips at NVIDIA. (includingGeForce/Tegra/Tesla/Quadro). Work on floorplan(from top level to block level). Power/clock distribution. Placement,...
23.06.2024
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Nvidia Senior Design Engineer Taiwan, Taiwan Province, Hsinchu
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Front-end design, quality checks for our display subsystem/IP. Co-work with verification engineers to ensure that the design is functional. Analyze design trade-offs and optimize design based on features, requirements, and...
23.06.2024
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Nvidia ASIC Verification Engineer - Hardware Taiwan, Taiwan Province, Hsinchu
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Micro-architecture definition for System-level modules (Fuse, Strap, Floorsweep, In-silicon measurement, Reset, Sysctrl, etc...). Unit-level and System-level verification for System-level modules. Own some NVIDIA internal checks to guarantee the design quality....
23.06.2024
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Nvidia Senior Mixed Signal Design Engineer Taiwan, Taiwan Province, Hsinchu
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Work with analog designers to create accurate systemVerilog model of analog components such as closed-loop PLL, Rx CTLE, SAR ADC and also optics components. You’ll work with system architects, digital...
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Description:Full job details
STA for hierarchical design. Constraints creation and validation, timing budget. Timing closure for both partition and full chip level. Special timing closure, such as io, test, clock etc. Synthesis, Netlist...
These jobs might be a good fit
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