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What you'll be doing:
In this position, you will expected to lead all block/chip level PD activities.
PD activities includes floor plans, abstract view generation, RC extraction, PNR, STA, EM,IR DROP, DRCs & schematic to layout verification. Work in collaboration with design team for addressing design challenges.
Help team members in debugging tool/design related issues.
Constantly look for improvement in RTL2GDS flow to improve PPA. Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention.
Responsible for all aspects of physical design and implementation of GPU and other ASICs targeted at the desktop, laptop, workstation, and mobile markets.
What we need to see:
BE/BTECH/MTECH, or equivalent experience.
4+ years of experience in Physical Design.
Strong understanding in the RTL2GDSII flow or design implementation in leading process technologies. Good understanding of the RTL2GDSII concepts related to synthesis, place & route, CTS, timing convergence, layout closure.
Expertise on high frequency design methodologies. Good knowledge and experience in Block-level and Full-chip Floor-planning and Physical verification. Working experience with tools like ICC2/Innovus, Primetime/Tempus etc used in the RTL2GDSII implementation.
Strong knowledge and experience in standard place and route flows ICC2/Synopsys and Innovus/Cadence flows preferred. Well versed with timing constraints, STA and timing closure.
Good automation skills in PERL, TCL, tool specific scripting on one of the industry leading Place & Route tools.
Ability to multi-task and flexibility to work in global environment.
Good communication skills and strong motivation, Strong analytical & Problem solving skills. Proficiency using Perl, Tcl, Make scripting is preferred.
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In this position, you will be expected to make architectural trade-offs based on features, performance requirements and system limitations, come up with micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean design. You will work with architects, other designers, pre- and post-silicon verification teams, synthesis, timing and backend teams to accomplish your tasks.
What you’ll be doing:
Own micro-architecture and RTL development of design modules.
Micro-architect features to meet performance, power and area requirements.
Work with HW architects to define critical features.
Collaborate with verification teams to verify the correctness of implemented features.
Co-operate with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable.
Interact with FPGA and S/W teams to prototype the design and ensure that S/W is tested.
Work on post-silicon verification and debug.
What we need to see:
BS / MS or equivalent experience.
5+ years of design experience.
Experience in RTL design of complex design units for at least two or three projects.
Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB).
Deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.
Expertise in Verilog.
Ways to stand out from the crowd:
Design experience in memory subsystem or network interconnect IP.
Good debugging and problem solving skills.
Scripting knowledge (Python/Perl/shell).
Leadership experience in leading small 2-3 member teams.
Good interpersonal skills and ability & desire to work as a part of a team.
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What you'll be doing:
Lead a team involved with development and delivery of Cumulus Linux packet forwarding andinfrastructurefeatures. Partner with other engineering teams to scope and develop solutions to improve systems security, performance and reliability features.
Lead a team to design, develop, test and maintain new functionality and improvements to existingfunctionalityrelated to packet forwarding and offload of L2, routing, ACLs, NAT, policy-based routing,VxLAN-EVPN.
Develop and debug C and Python code for packet forwarding monitoring, reliability and serviceability features as needed.
Collaborate with product, architecture, and engineering teams for End to End integration of systems infrastructure features into Linux and Cumulus Linux distribution
Work with project management team for effort estimation and planning of the features.
Work closely with recruiting staff to expand the team, including sourcing and interviewing candidates, participating in conferences/events, and onboarding new employees. Help engineers develop their careers, assigning them to projects tailored to their current skill levels as well as their long-term development, taking into account evolving strengths and capabilities
Work with upstream communities as needed, supervise technology trends like emerging standards for any technology opportunities.
Guide through the problem solving process, minimize how often problems take place and proactively take steps to prevent problems from happening
What we need to see:
Master of Science in Electrical Engineering, Computer Science, Computer Engineering or Bachelors (or equivalent experience)
10+ overall years of proven leadership in Linux systems, data center networking technologies; familiarity with datacenter protocols and 5 or more years of people management experience in an enterprise environment.
Familiar with cloud native concepts
Strong background with Linux OS feature development
Experience driving projects from concept to production
Excellent written and verbal communication and interpersonal skills. Comfortable articulating value propositions to customers and influencing internal teams
Experience with embedded software on network switches.
Background with bring up and troubleshooting of Ethernet Switching ASICs, Ethernet interfaces and modules
Ways to stand out from the crowd:
Strong background in Ethernet switching, Linux systems and Linux kernel networking
Experience with Merchant Silicon based platforms for Switching/Routing
Contributions to SONiC, SwitchDev or Switch Abstraction Interface (SAI) projects.
Knowledge of networking control plane operation in areas like IP, EVPN, Segment Routing etc.
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What you'll be doing:
You are encouraged to understand all features of a given project and define project milestones based on internal roadmaps, assign them and track them through agile framework
Define and develop system-level methodologies, tools, and IPs to build SOCs in an efficient and scalable manner.
Work on SOC Assembly and drive cross-functional teams towards SOC milestone execution.
Be responsible for integrating all the pieces for a given defined project milestone and deliver the model to relevant teams for further verification atcluster/sub-system/SOC/emulationlevels.
Have good grasp of Perl, Python, or other industry-standard scripting languages.
What we need to see:
BS (or equivalent experience) / MS with 5+ years of practical semiconductor design and architecture experience building complex SoC’s.
Must have firsthand experience & solid understanding of all phases of SOC development in multiple ASIC projects including ASIC architecture, Micro-Architecture, RTL design, verification, timing closure & Physical design.
Exposure to design and verification tools (Verilog/SV or equivalent, Cadence or equivalent simulation tools, debug tools like Indago, GDB etc.).
C/C++ programming or python or any other industry-standard scripting language experience desirable.
Experience working with software teams to tightly define the HW/SW interface including control/status registers, interrupt and error handling.
Hands on experience in successful tape outs of multiple complex, high-volume SoCs in advanced process nodes.
Exposure to various Chip Design Functions to be able to collaborate and solve complex cross functional problems.
Experience in synthesis, physical design and DFT is a plus & Experience in RTL Build and Design Automation is a plus.
Ways to Stand out from the crowd:
Chip lead type of technical leadership experience on delivering complex SOCs for enterprise and/or HPC applications.
Experience in RTL coding and debug, as well asperformance/power/areaanalysis and trade-offs
Experience working closely with physical design teams to develop highly optimized ASICs with excellent power, performance and area.
Prior experience of smartNIC and/or high-speed interconnect, strong coding skills in Perl, Python, or other industry-standard scripting languages.
SOC bring-up and post silicon validation experience
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What you'll be doing:
Lead and manage software engineers, including hiring, mentoring, and performance evaluations.
Define and implement a technical roadmap that closely aligns with company goals.
Coordinate the creation, advancement, and implementation of crucial platform services, promoting guidelines in software development, such as code reviews, testing, and documentation.
Encourage a culture centered on constant growth, originality, and outstanding technical proficiency.
Manage project timelines, resources, and risks to ensure successful delivery.
Provide operational and platform support during non-US business hours for service continuity and incident response.
What we need to see:
Bachelor's or equivalent experience in Computer Science, Engineering, or a related field.
10+ years of software development experience, with a focus on platform/backend systems, and 5+ years leading software engineering teams.
Demonstrated expertise in developing and rapidly growing distributed systems, cloud-native applications, and large-scale enterprise platforms for Configuration Management, Asset Management, and Observability.
Strong proficiency in programming languages such as Java, Python, or Go, and experience managing containerized application deployments in both cloud and on-prem environments.
Solid understanding of database technologies (both relational and NoSQL) and message queues.
Excellent communication, interpersonal, and leadership skills with a demonstrated ability to encourage, motivate, and drive technical excellence within agile development environments.
Ways to stand out from the crowd:
Experience with Nautobot to maintain asset lifecycle management for both On-Prem and Cloud Assets.
Hands-on skills in Python/Go Lang, with the ability to build and deploy containerized software on orchestration platforms.
Prior experience working with LLMs, RAGs, and the implementation of AIOps tools for incident diagnosis and remediation.
Experience in deploying Ansible Automation Platform and Salt Stack in On-Prem Hardware to manage Network and Infrastructure assets in Data Centers.
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What you'll be doing:
Your main responsibility will be to develop a technical and business strategy to win NVIDIA software and hardware platforms' adoption for the selected industries and verticals, mainly cloud focusing applications developers. The role requires a senior technical manager who believes that generative AI, deep learning, data science, and artificial intelligence is a new computing revolution and has the potential to transform every industry, with cloud first mind-set and strategy.
Develop India NVIDIA developer ecosystem with cross-functional team; Product, Engineering, Software team, Solution Architects, Business, Marketing, Inception and Sales.
Lead and develop strategic relationships with key startups, ISV’s, and leading industries’ developers.
Know all NVIDIA AI computing platforms from Datacenter, Cloud to Edge and effectively articulate the value proposition to the APAC developer community while driving and leading strategic partnerships and community building among Cloud developers by running webinar, workshops, developer session and hosting technical meetups.
Drive adoption of NVIDIA Cloud Native SDK’s and Software into developer products while being alert to the competitive landscape and communicate internally.
Be NVIDIA technology mentor, evangelize the NVIDIA HW and S/W Solutions by being the focal point for the software developer community and occasionally lend some hands-on technical support.
What we need to see:
Bachelor's Degree in Engineering, Science, Technical or other related discipline or equivalent experience
8+ years of experience. Master's or Ph.D’s is preferred.
Experience with cloud infrastructure platforms like AWS, Azure, Google Cloud, Tencent, Baidu, OCI, ByteDance, etc and hands-on exposure in cloud technologies and microservices architecture.
Understanding of virtualization and containerization technologies like Container, Docker, Kubernetes, VMware, KVM, etc.
Expertise in C, C++, Python programming languages and GenAI, Deep Learning, Machine Learning, 3D Design/Simulation frameworks, while has developed related Cloud applications.
Able to work independently and possess excellent communication skills to drive customer and internal engagements.
You will ensure a positive experience for external customers/developers and partners while working cross functionally within our organization.
Ways to stand out from the crowd:
Experience in developing various applications in cloud environments, covering various industry vertical.
Multi-year cloud-based development experience working on AI Deep Learning and Machine Learning Applications, AI Model Training/Inferencing and NVIDIA technologies and application domain.
Excellent organizational, planning, and execution skills.
Demonstrate ability to thrive in a dynamic environment that is experiencing rapid growth.
These jobs might be a good fit

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In this position, you will be encouraged to make architectural trade-offs based on features, performance requirements and system limitations, come up with micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean design. You will work with architects, other designers, pre- and post-silicon verification teams, synthesis, timing and backend teams to accomplish your tasks.
doing:
Own micro-architecture and RTL development of design modules.
Micro-architect features to meet performance, power and area requirements.
Work with HW architects to define critical features.
Collaborate with verification teams to verify the correctness of implemented features.
Interact with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable.
Co-operate with FPGA and S/W teams to prototype the design and ensure that S/W is tested.
Work on post-silicon verification and debug.
see:
BS / MS or equivalent experience.
4+ years of design experience.
Experience in micro-architecture and RTL development of complex designs.
Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB).
Deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping,, timing analysis, floor-planning, ECO, bring-up & lab debug.
Expertise in Verilog.
crowd:
Design experience in memory subsystem or network interconnect IP.
Good debugging and problem solving skills.
Scripting knowledge (Python/Perl/shell).
Good interpersonal skills and ability & desire to work as a part of a team.
These jobs might be a good fit

Share
What you'll be doing:
In this position, you will expected to lead all block/chip level PD activities.
PD activities includes floor plans, abstract view generation, RC extraction, PNR, STA, EM,IR DROP, DRCs & schematic to layout verification. Work in collaboration with design team for addressing design challenges.
Help team members in debugging tool/design related issues.
Constantly look for improvement in RTL2GDS flow to improve PPA. Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention.
Responsible for all aspects of physical design and implementation of GPU and other ASICs targeted at the desktop, laptop, workstation, and mobile markets.
What we need to see:
BE/BTECH/MTECH, or equivalent experience.
4+ years of experience in Physical Design.
Strong understanding in the RTL2GDSII flow or design implementation in leading process technologies. Good understanding of the RTL2GDSII concepts related to synthesis, place & route, CTS, timing convergence, layout closure.
Expertise on high frequency design methodologies. Good knowledge and experience in Block-level and Full-chip Floor-planning and Physical verification. Working experience with tools like ICC2/Innovus, Primetime/Tempus etc used in the RTL2GDSII implementation.
Strong knowledge and experience in standard place and route flows ICC2/Synopsys and Innovus/Cadence flows preferred. Well versed with timing constraints, STA and timing closure.
Good automation skills in PERL, TCL, tool specific scripting on one of the industry leading Place & Route tools.
Ability to multi-task and flexibility to work in global environment.
Good communication skills and strong motivation, Strong analytical & Problem solving skills. Proficiency using Perl, Tcl, Make scripting is preferred.
These jobs might be a good fit