Senior Architect Soc Modelling jobs at Nvidia in India, Bengaluru
Nvidia Senior Physical Design Engineer India, Karnataka, Bengaluru
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- India, Bengaluru
- India, Hyderabad
- time type
- Full time
- posted on
- Posted 5 Days Ago
- job requisition id
What you'll be doing:
In this position, you will expected to lead all block/chip level PD activities.
PD activities includes floor plans, abstract view generation, RC extraction, PNR, STA, EM,IR DROP, DRCs & schematic to layout verification. Work in collaboration with design team for addressing design challenges.
Help team members in debugging tool/design related issues.
Constantly look for improvement in RTL2GDS flow to improve PPA. Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention.
Responsible for all aspects of physical design and implementation of GPU and other ASICs targeted at the desktop, laptop, workstation, and mobile markets.
What we need to see:
BE/BTECH/MTECH, or equivalent experience.
4+ years of experience in Physical Design.
Strong understanding in the RTL2GDSII flow or design implementation in leading process technologies. Good understanding of the RTL2GDSII concepts related to synthesis, place & route, CTS, timing convergence, layout closure.
Expertise on high frequency design methodologies. Good knowledge and experience in Block-level and Full-chip Floor-planning and Physical verification. Working experience with tools like ICC2/Innovus, Primetime/Tempus etc used in the RTL2GDSII implementation.
Strong knowledge and experience in standard place and route flows ICC2/Synopsys and Innovus/Cadence flows preferred. Well versed with timing constraints, STA and timing closure.
Good automation skills in PERL, TCL, tool specific scripting on one of the industry leading Place & Route tools.
Ability to multi-task and flexibility to work in global environment.
Good communication skills and strong motivation, Strong analytical & Problem solving skills. Proficiency using Perl, Tcl, Make scripting is preferred.
These jobs might be a good fit
Nvidia Senior Architect GPU SoC Modelling India, Karnataka, Bengaluru
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- India, Bengaluru
- time type
- Full time
- posted on
- Posted Today
- job requisition id
What you'll be doing:
Modeling and analysis of graphics and / or SOC algorithms and features
Work in a matrixed environment, across the different modelling teams, to document, design, develop tools to analyze and simulate, validate, and verify models
Familiarize with the different models (functional and performance) that are used at Nvidia and help with feature implementation as required.
Develop tests, test plans, and testing infrastructure for newarchitectures/features.
Mentor younger engineers and help sustain good coding practices.
Learn about newer modelling techniques and frameworks, evaluate the best solution for our needs and work with your manager to drive the change
Help develop AI based tools to increase efficiency.
What we need to see:
Bachelors Degree (or equivalent experience) in a relevant discipline (Computer Science, Electrical Engineering or Computer Engineering)
8+ years of relevant work experience or MS with 5+ years of experience or PhD with 2+ years of experience
Strong programming ability: C++, C along with a good understanding of build systems (CMAKE, make), toolchains (GCC, MSVC) and libraries (STL, BOOST)
Computer Architecture background with experience in performance modeling with C++ and SystemC preferred
Familiarity with Docker, Jenkins, Python, Perl
Excellent communication and interpersonal skills and ability to work in a distributed team environment.
Nvidia Senior Verification Engineer Performance India, Karnataka, Bengaluru
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- India, Bengaluru
- time type
- Full time
- posted on
- Posted Today
- job requisition id
What will you be doing:
Responsibilities will include development of test plans and strategies, develop simulation environments, system bring-up, validation, and automation to deliver best-in-class CPUs.
Develop and maintain CPU simulator infrastructure, hardware CPU test and performance infrastructure.
Analyze and validate CPU and fabric performance, helping to understand current, and guide the development of future CPU products.
Definition and development of tool chain and workflows that enables the full system performance alignment.
Silicon based competitive analysis of NVIDIA CPUs.
What we need to see:
Master's or Bachelor's degree in EE/CS or equivalent experience
5+ years of experience preferably in the areas of CPU / SOC Performance Verification and Analysis
Strong understanding of computer system architecture and operating system fundamentals.
Hands-on experience with HDLs such as Verilog / System Verilog.
Knowledge of verification methodologies and tools for IP and SoC level verification.
Experience with System Verilog, C/C++, Python languages and relevant frameworks.
Background with debug on Silicon.
Ways to stand out from the crowd:
Detailed knowledge of the ARM and/or x-86 architecture.
Prior experience with performance analysis of CPUs.
Experience with analysis and characterization of CPU workloads.
Nvidia Senior GPU Compiler Development Engineer India, Karnataka, Bengaluru
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- India, Bengaluru
- India, Pune
- time type
- Full time
- posted on
- Posted 5 Days Ago
- job requisition id
What you will be doing:
Lead design and development of NVIDIA’s Assembler and Disassembler for GPU compute.
Work on binary analysis & instrumentation features like call graphs generation, program register usage and patching of GPU binaries
Work with GPU architecture and debugger/profiler development teams to understand their requirements and deliver new features & product improvements.
Collaborate closely with teams developing other related components to ensure compatibility, reliability, and high-quality code generation
Working with customers/partners to collect feedback and drive innovative ideas and features to incorporate into the product
What we need to see:
BS or MS degree in Computer Science, Computer Engineering, or related fields with 5+ years of experience in low-level system SW development and a minimum of 3 years related to assemblers, binary analysis tools, debuggers
Good analytical and C/C++ programming skills
Experience in any one area of compiler development including feature support, code generation and compiler infrastructure
Understanding of Assembly Language / Processor ISA (GPU ISA not required but a plus)
Knowledge of object file formats such as ELF and debugging formats (DWARF).
Ways to stand out from the crowd:
Understanding of debugger / profiler tools / bintools / Linker internals, experience in binary analysis / instrumentation tools like BOLT etc.
Usage of AI tools in everyday work like Cursor, Windsurf etc.
Knowledge of GPU development and compute APIs such as CUDA and OpenCL
Nvidia Senior System Software Engineer India, Karnataka, Bengaluru
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- India, Bengaluru
- time type
- Full time
- posted on
- Posted 6 Days Ago
- job requisition id
What you'll be doing:
Enable NVIDIA Cumulus Linux on next generation ASICs.
Define, design and develop features for NVIDIA Cumulus Linux.
Sustain the existing deployments of NVIDIA Cumulus Linux.
Working closely with customers to understand the pain points, new use cases, deployment strategies and come up with innovative solutions.
Translating requirements to the SDK and ASIC Engineers for enabling end-to-end solutions.
What we need to see:
Strong knowledge of forwarding path for L2 and L3 including concepts like ECMP etc.
Strong and proven experience in C and Python programming.
Worked with VxLAN and EVPN routing protocols.
Strong knowledge in areas of QoS, ACLs and VxLAN. And working knowledge of hardware resource management (tables, TCAMs, etc).
Battle scars from troubleshooting production network deployments.
BS or MS degree in Computer Engineering, Computer Science, or related degree, or equivalent experience.
5+ years of hands on experience.
Ways to stand out from the crowd:
Experience with Merchant Silicon for Switching/Routing.
Contributions to SONiC, SwitchDev or Switch Abstraction Interface (SAI) projects.
Nvidia Senior CAD Engineer India, Karnataka, Bengaluru
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- India, Bengaluru
- India, Hyderabad
- time type
- Full time
- posted on
- Posted 12 Days Ago
- job requisition id
What You’ll Be Doing:
Develop and maintain robust equivalence checking flows (FEC/FEV) for different stages of the VLSI design cycle, including RTL-to-RTL, RTL-to-Gate, and Gate-to-Gates equivalence checking.
Develop and enhance the RTL Physical-Synthesis work flows, both at full-chip and block-level.
Partner with implementation teams, on both synthesis and P&R side, to understand their requirements and pain-points if any, and enhance the methodology to cover for the same.
Develop and deploy various methodologies based on technology updates, design requirements, and tool-feature/version updates and bug-fixes.
Finetune the recipes for designs with aggressive PPA targets while ensuring logical-equivalence is maintained.
Optimize flows and methodologies for performance, capacity, and debug capabilities, ensuring efficient and effective verification of sophisticated VLSI designs.
Investigate and resolve equivalence checking issues, including setup and constraint-related problems, debug failures, and performance bottlenecks.
Develop custom scripts using tcl/perl/python to automate the post-processing of the reports/logs to present the results in a user-friendly format.
What We Need To See:
B.Tech/BS inVLSI/Electronics/ElectricalEngineering or Computer Science, with 5+ years of relevant ASIC design experience and/or CAD experience, with a focus on Logic Equivalence Checking and RTL-Synthesis.
Be familiar with Verilog and ASIC design flow along with experience in commercial EDA tools
Strong scripting skills in languages such as Perl, Python, and TCL.
Excellent problem-solving, debugging, and analytical skills.
Ability to work in a team environment and collaborate efficiently with multi-functional teams.
Strong communication and documentation skills
Nvidia Senior ASIC Design Engineer - XBAR IP India, Karnataka, Bengaluru
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- India, Bengaluru
- time type
- Full time
- posted on
- Posted Today
- job requisition id
In this position, you will be expected to make architectural trade-offs based on features, performance requirements and system limitations, come up with micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean design. You will work with architects, other designers, pre- and post-silicon verification teams, synthesis, timing and backend teams to accomplish your tasks.
What you’ll be doing:
Own micro-architecture and RTL development of design modules.
Micro-architect features to meet performance, power and area requirements.
Work with HW architects to define critical features.
Collaborate with verification teams to verify the correctness of implemented features.
Co-operate with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable.
Interact with FPGA and S/W teams to prototype the design and ensure that S/W is tested.
Work on post-silicon verification and debug.
What we need to see:
BS / MS or equivalent experience.
5+ years of design experience.
Experience in RTL design of complex design units for at least two or three projects.
Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB).
Deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.
Expertise in Verilog.
Ways to stand out from the crowd:
Design experience in memory subsystem or network interconnect IP.
Good debugging and problem solving skills.
Scripting knowledge (Python/Perl/shell).
Leadership experience in leading small 2-3 member teams.
Good interpersonal skills and ability & desire to work as a part of a team.
- India, Bengaluru
- India, Hyderabad
- time type
- Full time
- posted on
- Posted 5 Days Ago
- job requisition id
What you'll be doing:
In this position, you will expected to lead all block/chip level PD activities.
PD activities includes floor plans, abstract view generation, RC extraction, PNR, STA, EM,IR DROP, DRCs & schematic to layout verification. Work in collaboration with design team for addressing design challenges.
Help team members in debugging tool/design related issues.
Constantly look for improvement in RTL2GDS flow to improve PPA. Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention.
Responsible for all aspects of physical design and implementation of GPU and other ASICs targeted at the desktop, laptop, workstation, and mobile markets.
What we need to see:
BE/BTECH/MTECH, or equivalent experience.
4+ years of experience in Physical Design.
Strong understanding in the RTL2GDSII flow or design implementation in leading process technologies. Good understanding of the RTL2GDSII concepts related to synthesis, place & route, CTS, timing convergence, layout closure.
Expertise on high frequency design methodologies. Good knowledge and experience in Block-level and Full-chip Floor-planning and Physical verification. Working experience with tools like ICC2/Innovus, Primetime/Tempus etc used in the RTL2GDSII implementation.
Strong knowledge and experience in standard place and route flows ICC2/Synopsys and Innovus/Cadence flows preferred. Well versed with timing constraints, STA and timing closure.
Good automation skills in PERL, TCL, tool specific scripting on one of the industry leading Place & Route tools.
Ability to multi-task and flexibility to work in global environment.
Good communication skills and strong motivation, Strong analytical & Problem solving skills. Proficiency using Perl, Tcl, Make scripting is preferred.
These jobs might be a good fit
