Mask Designer jobs at Nvidia in India, Bengaluru

What you'll be doing:

• Execute IC layout of cutting edge, high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 2nm, 3nm, 5nm, 7nm and lower nodes following industry best practices.

• Be responsible for and optimize all physical verification activities, including DRC, LVS, density analysis, and comprehensive tape-out checks.

• Drive the identification and resolution of complex physical design issues in layouts, mentoring junior engineers in established methodologies.

• Development of analog layouts, leading solving efforts and driving optimization for performance, area, and manufacturability.

• Cultivate effective teamwork across multi-functional teams, influencing project direction and ensuring alignment with organizational objectives.

• Excel in resource management, representing the team in technical discussions with customers

• Lead and perform full custom layout of analog/mixed-signal blocks such as op-amps, bandgaps, PLLs, ADCs, DACs, LDOs, Voltage Regulators etc.

• Ensure design quality by adhering to matching, symmetry, and parasitic sensitivity requirements.

What we need to see:

• 8+ years of experience in high performance analog layout in advanced CMOS process.

• BE/M-Tech in Electrical & Electronics or equivalent experience.

• Thorough knowledge of industry standard EDA tools for Cadence.

• Experience with layout of high-performance analog blocks such as Current mirrors, Sense Amps, bandgaps etc. is required.

• Knowledge in analog design and layout guidelines, high speed IO, (matching devices, symmetrical layout, signal shielding, other analog specific guidelines)

• Experience with floor planning, block level routing and macro level assembly.

• Knowledge of high-performance analog layout techniques such as common centroid layout, matching, symmetrical layout, signal shielding, use of dummy devices, thermal aware layout with consideration for electro migration and other analog specific guidelines.

• Demonstrated experience with analog layout for silicon chips in mass production.

• Background with sub-micron design in foundry CMOS nodes 7nm finfet and below is preferred.

• Experience working in distributed design team is a plus.

What you'll be doing:

• Execute IC layout of cutting edge, high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 2nm, 3nm, 5nm, 7nm and lower nodes following industry best practices.

• Deliver layouts for Circuit Solutions Group specializing in digital cum analog IPs.

• IP layout will comprise of significant digital components and some analog components.

• Adopting and putting in place best layoutpractices/methodologyfor composing Analog and digital layouts

• Follow company procedures and practices for IC layout activities.

• Perform full custom layout of analog/mixed-signal blocks such as op-amps, bandgaps, PLLs, ADCs, DACs, LDOs, Voltage Regulators etc.

• Ensure design quality by adhering to matching, symmetry, and parasitic sensitivity requirements.

• Execute layout verification (DRC, LVS, ERC, Antenna checks, EMIR) and resolve violations.

• Optimize layouts for area, performance, and manufacturability.

What we need to see:

• 4+ years of experience in high performance analog layout in advanced CMOS process.

• BE/M-Tech in Electrical & Electronics or equivalent experience.

• Thorough knowledge of industry standard EDA tools for Cadence.

• Experience with layout of high-performance analog blocks such as Current mirrors, Sense Amps, bandgaps etc. is required.

• Knowledge in analog design and layout guidelines, high speed IO, (matching devices, symmetrical layout, signal shielding, other analog specific guidelines)

• Experience with floor planning, block level routing and macro level assembly.

• Knowledge of high-performance analog layout techniques such as common centroid layout, matching, symmetrical layout, signal shielding, use of dummy devices, thermal aware layout with consideration for electro migration and other analog specific guidelines.

• Demonstrated experience with analog layout for silicon chips in mass production.

• Background with sub-micron design in foundry CMOS nodes 7nm finfet and below is preferred.

• Experience working in distributed design team is a plus.

• Requires self-starter with the ability to define and adhere to a schedule.

What you'll be doing:

• Implement IC layout of innovative, high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm,5nm, 7nm and lower nodes following industry standard methodologies.

• Lead the architecture and layout design of key memory subsystems, including control logic, sense amplifiers, I/O blocks, bit-cell arrays, and decoders for advanced technology nodes.

• Direct custom layout and verification of complex memory cells, setting standards and methodologies for compiler-driven design flows.

• Be responsible for and optimize all physical verification activities, including DRC, LVS, density analysis, and comprehensive tape-out checks.

• Drive the identification and resolution of complex physical design issues in compiler-generated layouts, mentoring junior engineers in established methodologies.

• Provide guidance on IR drop and EM mitigation strategies, establishing design methodologies for robust memory layouts.

• Possess deep expertise in ultra-deep sub-micron layout challenges, regularly innovating and implementing advanced solutions.

• Development of memory compilers, leading solving efforts and driving optimization for performance, area, and manufacturability.

• Cultivate effective teamwork across multi-functional teams, influencing project direction and ensuring alignment with organizational objectives.

• Excel in resource management, representing the team in technical discussions with customers

What we need to see:

• B.E/B Tech. / M Tech in Electronics or equivalent experience with 8+ Years of proven experience in Memory layout in advanced CMOS process.

• Detailed knowledge of industry standard EDA tools for Cadence.

• Experience with layout of high-performance memories of various types.

• Knowledge of Layout basics including the various types of bitcells, Decoder, LIO etc. (matching devices, symmetrical layout, signal shielding)

• Experience with floor planning, block level routing and macro level assembly.

• Detailed knowledge of top level verification including the EM/IR quality checks and detailed knowledge of layout dependent effects including LOD, Dummification, fills etc.

What you'll be doing:

• Implement IC layout of innovative, high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm,5nm, 7nm and lower nodes following industry standard methodologies.

• Lead the architecture and layout design of key memory subsystems, including control logic, sense amplifiers, I/O blocks, bit-cell arrays, and decoders for advanced technology nodes.

• Direct custom layout and verification of complex memory cells, setting standards and methodologies for compiler-driven design flows.

• Be responsible for and optimize all physical verification activities, including DRC, LVS, density analysis, and comprehensive tape-out checks.

• Drive the identification and resolution of complex physical design issues in compiler-generated layouts, mentoring junior engineers in established methodologies.

• Provide guidance on IR drop and EM mitigation strategies, establishing design methodologies for robust memory layouts.

• Possess deep expertise in ultra-deep sub-micron layout challenges, regularly innovating and implementing advanced solutions.

• Development of memory compilers, leading solving efforts and driving optimization for performance, area, and manufacturability.

• Cultivate effective teamwork across multi-functional teams, influencing project direction and ensuring alignment with organizational objectives.

• Excel in resource management, representing the team in technical discussions with customers

• IP layout will comprise of significant digital components.

• Adopting and putting in place the best layoutpractices/methodologyfor composing digital Memory layouts

• Follow company procedures and practices for IC layout activities.

What we need to see:

• B.E/B Tech. / M Tech in Electronics or equivalent experience with 2+ years of proven experience in Memory layout in advanced CMOS process.

• Detailed knowledge of industry standard EDA tools for Cadence.

• Experience with layout of high-performance memories of various types.

• Knowledge of Layout basics including the various types of bitcells, Decoder, LIO etc. (matching devices, symmetrical layout, signal shielding)

• Experience with floor planning, block level routing and macro level assembly.

• Detailed knowledge of top level verification including the EM/IR quality checks and detailed knowledge of layout dependent effects including LOD, Dummification, fills etc.

What you'll be doing:

• Implement IC layout of innovative, high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm,5nm, 7nm and lower nodes following industry standard methodologies.

• Lead the architecture and layout design of key memory subsystems, including control logic, sense amplifiers, I/O blocks, bit-cell arrays, and decoders for advanced technology nodes.

• Direct custom layout and verification of complex memory cells, setting standards and methodologies for compiler-driven design flows.

• Be responsible for and optimize all physical verification activities, including DRC, LVS, density analysis, and comprehensive tape-out checks.

• Drive the identification and resolution of complex physical design issues in compiler-generated layouts, mentoring junior engineers in established methodologies.

• Provide guidance on IR drop and EM mitigation strategies, establishing design methodologies for robust memory layouts.

• Possess deep expertise in ultra-deep sub-micron layout challenges, regularly innovating and implementing advanced solutions.

• Development of memory compilers, leading solving efforts and driving optimization for performance, area, and manufacturability.

• Cultivate effective teamwork across multi-functional teams, influencing project direction and ensuring alignment with organizational objectives.

• Excel in resource management, representing the team in technical discussions with customers

• IP layout will comprise of significant digital components.

• Adopting and putting in place the best layoutpractices/methodologyfor composing digital Memory layouts

• Follow company procedures and practices for IC layout activities.

What we need to see:

• B.E/B Tech. / M Tech in Electronics or equivalent experience with 2+ years of proven experience in Memory layout in advanced CMOS process.

• Detailed knowledge of industry standard EDA tools for Cadence.

• Experience with layout of high-performance memories of various types.

• Knowledge of Layout basics including the various types of bitcells, Decoder, LIO etc. (matching devices, symmetrical layout, signal shielding)

• Experience with floor planning, block level routing and macro level assembly.

• Detailed knowledge of top level verification including the EM/IR quality checks and detailed knowledge of layout dependent effects including LOD, Dummification, fills etc.

What you'll be doing:

• Implement IC layout of innovative, high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm,5nm, 7nm and lower nodes following industry standard methodologies.

• Deliver layouts for Full Custom Memory group specializing in digital Memory circuits.

• IP layout will comprise of significant digital components.

• Adopting and putting in place the best layoutpractices/methodologyfor composing digital Memory layouts

• Follow company procedures and practices for IC layout activities.

What we need to see:

• B.E/B Tech. / M Tech in Electronics or equivalent experience with 5+ Years of proven experience in Memory layout in advanced CMOS process.

• Detailed knowledge of industry standard EDA tools for Cadence.

• Experience with layout of high-performance memories of various types.

• Knowledge of Layout basics including the various types of bitcells, Decoder, LIO etc. (matching devices, symmetrical layout, signal shielding)

• Experience with floor planning, block level routing and macro level assembly.

• Detailed knowledge of top level verification including the EM/IR quality checks and detailed knowledge of layout dependent effects including LOD, Dummification, fills etc.