Asic Verification Engineer jobs at Nvidia in India, Bengaluru

What you’ll be doing:

• Own ASIC verification of IP/Cluster for complicated designs in RTL.

• Work with HW architects and designers to make the right implementation choices.

• Interact with the Performance verification teams to augment verification through dynamic simulations and/or Formal verification techniques.

• You will work with the specifications and ensure functional and code coverage of all the RTL which you will verify.

• Partner with and enable FPGA and S/W teams to ensure that S/W is tested.

• Be involved with post-silicon verification and debug.

What we need to see:

• BS / MS or equivalent experience.

• 2+ years of design experience.

• Experience in ASIC verification of complex design units for at least one or two projects.

• Background with design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB).

• Exposure to System Verilog and UVM based methodology for ASIC verification is highly desired.

Ways to stand out from the crowd:

• Knowledge of Memory controllers or prior experience with verification of IP/clusters involving access to Memory.

• Good debugging and problem solving skills.

• Scripting knowledge (Python/Perl/shell).

• Good interpersonal skills and ability & desire to work as a part of a team.

What you will be doing:

• Lead design and development of NVIDIA’s Assembler and Disassembler for GPU compute.

• Work on binary analysis & instrumentation features like call graphs generation, program register usage and patching of GPU binaries

• Work with GPU architecture and debugger/profiler development teams to understand their requirements and deliver new features & product improvements.

• Collaborate closely with teams developing other related components to ensure compatibility, reliability, and high-quality code generation

• Working with customers/partners to collect feedback and drive innovative ideas and features to incorporate into the product

What we need to see:

• BS or MS degree in Computer Science, Computer Engineering, or related fields with 5+ years of experience in low-level system SW development and a minimum of 3 years related to assemblers, binary analysis tools, debuggers

• Good analytical and C/C++ programming skills

• Experience in any one area of compiler development including feature support, code generation and compiler infrastructure

• Understanding of Assembly Language / Processor ISA (GPU ISA not required but a plus)

• Knowledge of object file formats such as ELF and debugging formats (DWARF).

Ways to stand out from the crowd:

• Understanding of debugger / profiler tools / bintools / Linker internals, experience in binary analysis / instrumentation tools like BOLT etc.

• Usage of AI tools in everyday work like Cursor, Windsurf etc.

• Knowledge of GPU development and compute APIs such as CUDA and OpenCL

What you'll be doing:

• Enable NVIDIA Cumulus Linux on next generation ASICs.

• Define, design and develop features for NVIDIA Cumulus Linux.

• Sustain the existing deployments of NVIDIA Cumulus Linux.

• Working closely with customers to understand the pain points, new use cases, deployment strategies and come up with innovative solutions.

• Translating requirements to the SDK and ASIC Engineers for enabling end-to-end solutions.

What we need to see:

• Strong knowledge of forwarding path for L2 and L3 including concepts like ECMP etc.

• Strong and proven experience in C and Python programming.

• Worked with VxLAN and EVPN routing protocols.

• Strong knowledge in areas of QoS, ACLs and VxLAN. And working knowledge of hardware resource management (tables, TCAMs, etc).

• Battle scars from troubleshooting production network deployments.

• BS or MS degree in Computer Engineering, Computer Science, or related degree, or equivalent experience.

• 5+ years of hands on experience.

Ways to stand out from the crowd:

• Experience with Merchant Silicon for Switching/Routing.

• Contributions to SONiC, SwitchDev or Switch Abstraction Interface (SAI) projects.

What You’ll Be Doing:

• Develop and maintain robust equivalence checking flows (FEC/FEV) for different stages of the VLSI design cycle, including RTL-to-RTL, RTL-to-Gate, and Gate-to-Gates equivalence checking.

• Develop and enhance the RTL Physical-Synthesis work flows, both at full-chip and block-level.

• Partner with implementation teams, on both synthesis and P&R side, to understand their requirements and pain-points if any, and enhance the methodology to cover for the same.

• Develop and deploy various methodologies based on technology updates, design requirements, and tool-feature/version updates and bug-fixes.

• Finetune the recipes for designs with aggressive PPA targets while ensuring logical-equivalence is maintained.

• Optimize flows and methodologies for performance, capacity, and debug capabilities, ensuring efficient and effective verification of sophisticated VLSI designs.

• Investigate and resolve equivalence checking issues, including setup and constraint-related problems, debug failures, and performance bottlenecks.

• Develop custom scripts using tcl/perl/python to automate the post-processing of the reports/logs to present the results in a user-friendly format.

What We Need To See:

• B.Tech/BS inVLSI/Electronics/ElectricalEngineering or Computer Science, with 5+ years of relevant ASIC design experience and/or CAD experience, with a focus on Logic Equivalence Checking and RTL-Synthesis.

• Be familiar with Verilog and ASIC design flow along with experience in commercial EDA tools

• Strong scripting skills in languages such as Perl, Python, and TCL.

• Excellent problem-solving, debugging, and analytical skills.

• Ability to work in a team environment and collaborate efficiently with multi-functional teams.

• Strong communication and documentation skills