Soc Performance Architect jobs at Intel

Job Description:

In this role, you will have the opportunity to work on cutting edge technology, use best in class systems and equipment. We expect you to have good scripting skills and be able to process large amounts of performance data, use automation for analyzing and optimizing Graphics performance. You will also work closely with cross-functional teams to ensure our SoCs meet the highest standards of performance, power efficiency and identifying opportunities for improvement.

Qualifications:

Minimum qualifications are required to be initially considered for this position. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and orschoolwork/classes/research.

Minimum Qualifications

• Bachelor's degree with 3+ years of experience or Master's degree with 2+ years of experience in Electrical Engineering, Computer Engineering or related field.

• Post-silicon validation using test equipment, computer systems, and test station Software development.

• Experience with scripting languages such as Python, C/C++ and/or Perl.

Preferred Qualifications:

• CPU micro-architectural and/or high-speed bus protocol experience.

• Experience in design, verification or validation disciplines, system/platform level debug and root cause isolation, methodology and tools.

• Experience with Power measurement and debug tools

• Experience with leading Automation efforts, planning, execution and overseeing system validation activities.

• Deep technical knowledge in performance and power management including understanding of architecture and microcode sufficient to understand potential Power and performance impacts of changes.

• Familiarity with industry benchmarks, which aspects of performance they measure and competitive analysis from previous gen products.

• Experience with Performance counters.

Experienced HireShift 1 (United States of America)US, California, Folsom
Position of Trust

offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Key Responsibilities:

• Lead the co-design of silicon and package, focusing on DDR PHY and mixed signal IP integration for server SOCs.
• Design bump maps, floor plans, and manage area constraints for PHYs, collaborating closely with packaging technical experts.
• Conduct hands-onpackage extractionsand simulations(signal integrity, power integrity)
• Finalize bump-out, floor plan, and area decisions at the end of tech readiness phases.
• Interface with packaging teams on advanced technologies (e.g., C4 bumps, micro bumps, EMIB, hybrid bonding as needed).
• Focus on design, development, and architecture, not process or materials engineering.

Required Experience:

• Experience in both silicon design (preferably mixed signal/analog) and packaging co-design.
• Background in DDR, SOC, or similar high-speed interface development.
• Hands-on expertise with bump mapping, floor planning, and packaging constraints.
• Proven ability to collaborate across silicon and packaging teams, including risk assessment and simulation.
• Familiarity with advanced packaging technologies (hybrid bonding, EMIB, etc.) is a plus but not required.
• Individual contributor or principal engineer level preferred; management experience is not required.
• Experience at leading companies in advanced packaging and PHY design (e.g., Apple, Broadcom, Qualcomm, Micron, AMD, Nvidia).

Qualifications:

• Bachelors in electrical engineering, chemical engineering, mechanical engineering, material science or similar field (Master’s or Ph.D. preferred).
• 10+ years in silicon and packaging co-design

Experienced HireShift 1 (United States of America)US, California, FolsomUS, Arizona, Phoenix, US, California, Santa Clara, US, Oregon, Hillsboro
Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

Job Description:

About the Role: We are seeking a highly experienced Senior Software Expert specializing in SoC Power and Performance Architecture to join our innovative team. In this pivotal role, you will leverage your expertise to enhance the power efficiency and performance of our System-on-Chip (SoC) designs. You will collaborate with cross-functional teams to ensure our SoCs achieve optimal performance and power efficiency, while identifying and implementing opportunities for improvement. You will also be setting simulation methodologies and driving those across the teams.

Key Responsibilities:
• Power and Performance Optimization: Lead and drive initiatives to optimize SoC power and performance through advanced software techniques, including firmware tuning, workload analysis, and architectural design modifications.
• Collaboration: Partner with architects, design engineers, validation teams, and marketing to deliver industry-leading SoC solutions, providing software insights and expertise.
• Pre-Silicon Planning: Define and implement detailed power and performance tools and methodologies in the pre-silicon phase, focusing on software architecture and design.
• DevOps Pipeline Establishment: Develop and establish DevOps pipelines for power, performance, and thermal architecture tools and methodologies, ensuring efficient and automated workflows.
• Simulation Technologies: Establish and implement simulation technologies and methodologies to predict and analyze power, performance, and thermal characteristics.
• Simulation Model Development: Develop and refine simulation models for power, performance, and thermal analysis, enabling accurate and predictive assessments of SoC designs.

Qualifications:

Minimum Qualifications:

• Bachelor's degree with 7+ years of experience or
• Master's degree with 5+ years of experience, or
• PhD with 2+ years of experience in Electrical Engineering, Computer Engineering, or a related field.

Preferred Qualifications:

• In-depth knowledge of CPU architecture, benchmarks, power management, and memory sub-system validation.
• Extensive experience in simulation development in the pre-RTL phase.
• Strong background in SW architecture and quality.
• Proficiency in developing simulation models for SoC.
• Advanced software development skills, including experience with scripting languages such as Python, C++.
• Deep understanding and experience with operating systems.
• Expertise in statistical data analysis and design of experiments.
• Familiarity with industry benchmarks, understanding the aspects of performance they measure, and conducting competitive analysis from previous generation products.

Experienced HireShift 1 (United States of America)US, Oregon, HillsboroUS, Arizona, Phoenix, US, California, Folsom, US, California, Santa Clara
Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

The job Develops the logic design, register transfer level (RTL) coding, and simulation for graphics IPs (including graphics, compute, display, and media) required to generate cell libraries, functional units, and the GPU IP block for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly across verification hierarchies, drives unit level verification, and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high quality integration of the GPU block.

As ayour responsibilities will include but are not limited to:

• You will be responsible for designing and/or integrating IP for a discrete graphics SoC. You will be working or assisting in architecture, design, implementation, formal verification, emulation and validation of discrete graphics SoC products, including:

• Creating a design to produce key assets that help improve product KPIs for discrete graphics products.

• Working with SoC Architecture and platform architecture teams to establish silicon requirements.

• Making appropriate design trade off balancing risk, area, power, performance, validation complexity and schedule.

• Creating micro architectural specification document for the design.

• Working with external vendors on tools or IPs required for the development of micro-architecture, design and design qualification of custom silicon designs.

• Driving vendor's methodology to meet world class silicon design standards.

• Architecting area and power efficient low latency designs with scalabilities and flexibilities.

• Power and Area efficient RTL logic design and DV support.

• Running tools to ensure lint-free and CDC/RDC clean design, VCLP.

• Synthesis and timing constraints.

The ideal candidate will exhibit the following behavioral traits:

• Ability to drive and improve digital design methodology to achieve high quality first silicon

• Able to work with multi-functional teams within Intel and external vendors across geographical boundaries to resolve architectural and implementation challenges with a focus on schedule

• Strong verbal and written communication skills

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimumqualifications:

• Bachelors degree in Electrical, Computer Engineering with 4+ Years relevant experience in the semiconductor industry.

• OR Masters degree in Elecrtical, Computer Engineering with 3+ years relevant experience in the semiconductor industry

• 4+ years of experience in/with:

  • Verilog and system verilog, synthesizeable RTL

  • Modern design techniques and energy-efficient/low power logic design and power analysis

  • Computer Architecture

Preferred qualifications:

• Experience with FPGA emulation, silicon bring-up, characterization and debug

• Experience in multiple tape-outs reaching production with first pass silicon

Experienced HireShift 1 (United States of America)US, California, FolsomUS, California, Santa Clara

Benefits:

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

Key Responsibilities

• Architectural Leadership: Lead the architectural definition and integration of high-speed PHYs for client SoCs, including PCIe, CXL, USBx (e.g., eUSB2, USB3, USB4), Display, MIPI (D-PHY, C-PHY, M-PHY), Ethernet, and TSN. Collaborate with platform and product architects to analyze requirements and define critical performance, power, and area specifications to ensure the success of our products.
• IP Evaluation: Conduct technical evaluations of both internal and external PHY IPs, analyzing their performance characteristics against product requirements, and ensuring strategic alignment with overall product goals. Define detailed IP requirements, lead vendor engagement, and make strategic IP selection recommendations based on technical feasibility, cost-effectiveness, and long-term roadmap alignment.
• Technology Vision: Proactively research and evaluate emerging high-speed I/O technologies, industry trends, and evolving standards. Identify and champion opportunities to incorporate these advancements into our product roadmap, enhancing performance, power efficiency, and feature sets, and positioning our products for competitive advantage.
• Technical Documentation: Create clear and comprehensive architecture specifications and rigorous integration guidelines. Provide review and constructive feedback on related architectural specifications to ensure alignment with overall SoC goals.
• Technical Mentorship and Collaboration: Provide technical guidance and mentoring to junior engineers, fostering their growth and contributing to the overall team expertise. Champion a collaborative environment across multiple teams.
• Post-Silicon Leadership: Serve as a technical lead in the post-silicon debug and validation of high-speed I/O interfaces, leading taskforces and driving the resolution of complex issues. Oversee the validation process to ensure seamless and high-quality implementations.

Additional Skills:

• Demonstrated strategic acumen with proven effectiveness in collaborating with senior technologists and business leaders across organizational boundaries.• Demonstrated ability to network with and influence a broad range of stakeholders

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications:•

• BS degree in Electrical/Computer Engineering with a minimum of 15 years of experience.
• Master's or PhD degree in Electrical/Computer Engineering with minimum 12 years of experience
  

Preferred Qualifications:

• High familiarity with industry trends within the HSIO domain and the ability to map them to Intel roadmap/products and segment strategies.
• We look forward to welcoming a dynamic and innovative High-Speed I/O (PHY) Architect to our team. Apply now and be a part of shaping the future of our client SoC technology.
• Prior hands-on experience in High-Speed IO PHY Architecture and Design.
• Strong knowledge in the interoperability of HSIO PHYs within the PCIe, SATA, Ethernet, USB2, USB3, USB4, Display or MIPI IO Controller subsystems
• Strong technical leadership and communication skills

Experienced HireShift 1 (United States of America)US, California, FolsomUS, Arizona, Phoenix, US, California, Santa Clara, US, Oregon, Hillsboro
Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

Your responsibilities may include but not be limited to:

• Define SoC fabrics, SoC hardware/software interface, and IP integration.

• Author high-level architecture specifications that meet product/market requirements and facilitate correct implementation by development teams

• Interact with Micro Architects, IP Architects, discrete GFX team, RTL Design teams, Verification teams, Emulation team, Power and Performance validation teams to understand the product requirements and define overall Display strategy to ensure the end product meets the PnP goals at pre-silicon estimation and post-silicon measurement.

• Interact withapplication/driver/firmware

The SOC Architect should possess the following attributes:

• Excellent written and verbal communication skills.

• Willingness to work effectively in a collaborative, cross-functional environment.

• Excellent problem-solving and debugging skills.

• Willingness to lead task forces to resolve problems.

Qualifications:

Bachelor's degree in Computer Science, Computer Engineering, or Electrical Engineering with:

• BS degree with 8+ years of industry experience

• OR- Master's degree with 6+ years of industry experience

• OR- PhD degree with 4+ years of industry experience

Candidate must have combined 4+ years of experience in the following areas:

• System-on-Chip (SoC) integration,

• SoC architecture,

• SoC design,

• System architecture ( such as Hardware / Software interface, PNP )

Preferred Qualifications:

• IP integration and SoC flows with IP's such as Graphics, Media, or Image Processing.

• Broad knowledge of computer systems (software, hardware, firmware, silicon).

• Experience with hardware/software interfaces.

• Power and Performance.

• Experience with at least one of the following: Memory controllers, cache hierarchy, fabrics, high speed I/O protocols.

Experienced HireShift 1 (United States of America)US, Oregon, HillsboroUS, California, Folsom, US, California, Santa Clara
Position of Trust

offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

Responsibilities include:

• Develops complex code with C++ templates for optimal GPU kernels.
• Understand PyTorch or Similar framework’s usage of AI kernels and design the interfaces.
• Interacts with partner teams to understand the requirements and convert to tangible action items for development.
• Develop architectural documents for setting direction to larger team.

Behavioral traits that we are looking for:

• Excellent written and oral communication skills including technical details and concepts.
• Willingness to lead large teams of engineers with clear direction of complex requirements.
• Willingness adhering to specific timelines and delivering quality SW products.

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and orschoolwork/classes/research.

Minimum Qualifications:

• Bachelor’s degree and 6+ years or Master’s degree and 4+ years’ experience or Ph.D and 2+ years of experience in Computer Engineering, Computer Science, Data Science, Software Engineering, Electronic Engineering, Physics, Mathematics, Aerospace engineering, applied mathematics, mechanical engineering, or related technical disciplines.
• 3+ years of experience in complex C++ template-based development such as meta level programming.
• 2+ years’ experience with GPU architecture.
• 2+ years’ experience SYCL / CUDA knowledge.
• 1+ years’ experience with GEMM kernels.

How to stand out from other candidates (Preferred Qualifications):

• AI kernel developments (such as flash attention, MoE),
• Understanding of overall AI SW stack,
• Understanding of PyTorch architecture.

Our total rewards package goes above and beyond just a paycheck. Whether you're looking to build your career, improve your health, or protect your wealth, we offer generous benefits to help you achieve your goals. Go to

Experienced HireShift 1 (United States of America)US, Oregon, HillsboroUS, California, Santa Clara
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.