Soc High-speed I/o Phy Architect jobs at Intel

Job Description:

Since pioneering the world’s first hybrid silicon laser, IPS has led the industry in scalable, high-volumemanufacturing andadvanced photonics development. Our mission: deliver next-generation bandwidth growth with smaller form factors, co-packaging, and speeds from 400G today to 1.6T+ tomorrow.

We are seeking a Lead Analog SerDes Architect / Design Engineer to join our team and shape the future of data center connectivity. In this role, you will:

• Defining circuit architecture and enabling designs meeting power, and performance for next generation optical interconnects based on system specifications.
• As part of the team developing key integrated circuit components the engineer must be able to work collaboratively leading block level development.
• Specify, architect and design low voltage and low power Mixed-Signal integrated circuits and work collaboratively with digital designers.
• Plan design work with constraints on performance, schedule and quality.
• Provide guidance to junior designers and layout engineers.
• Guidance to develop test plans for post-silicon characterization.
• Document all design work with review materials and detailed design descriptions.

Minimum QualificationsThe ideal candidate should have a minimum of MS in Electrical Engineering with 8+ years of experience in high-speed serial links and deep knowledge of analog CMOS/BiCMOS designs in deep sub-micron process technologies.• Hands-on circuit design experience of SerDes blocks like Equalizers, PLL, Phase-Interpolators, CDR, etc. for 28Gbps+ data rates.
• Experience with design of inductors, transmission line, Trans-Impedance Amplifiers (TIA) and modulator drivers.
• Experience with design of precision analog circuits like ADC/DACs.
• Experience with designing PAM4/NRZ links.
• Experience with Mixed signal design flow
• Experience with full-chip designs, ESDs and verification flows.
Preferred Qualifications
• Familiarity with Optical communications.
• Experience with 400G/800G/1.6T optical links.
• Experience with package/test setup design.

Experienced HireShift 1 (United States of America)US, California, Santa Clara
Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 214,730.00 USD - 303,140.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

WHO YOU ARE

Responsibilities include, but are not limited to:

• Performs functional logic verification of an integrated SoC to ensure design will meet specifications.

• Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications.

• Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs.

• Replicates, root causes, and debugs issues in the presilicon environment.

• Finds and implements corrective measures to resolve failing tests.

• Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features.

• Documents test plans and drive technical reviews of plans and proofs with design and architecture teams.

• Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage.

• Maintains and improves existing functional verification infrastructure and methodology.

• Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages and proliferates to future products.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Bachelor’s degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field with 1+ years of relevant experience

— or —

Master’s degree in the same fields

Relevant work experience should be of the following:

• Experience with UVM
• Experience with System Verilog
• Experience with Design Verification
• Experience with Computer Architecture
• Experience with Hardware Verification

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and orschoolwork/classes/research.

College GradShift 1 (United States of America)Virtual US
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 90,890.00 USD - 170,890.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. However, you must live and work from the country specified in the job posting, in which Intel has a legal presence. Due to legal regulations, remote work from any other country is unfortunately not permitted. * Job posting details (such as work model, location or time type) are subject to change.The application window for this job posting is expected to end by 11/25/2026

Job Description:

In this position, you will function as a senior technical member in the NPU architecture performance COE(center-of-excellence)

The role’s responsibilities include but are not limited to:

• Define performance model architecture and modeling flow to best reflect the interworking of NPU SW/HW.
• Implementing and testing performance models with systematic SW development practice.
• Conductperformance-and-poweranalysis of various neural network workloads.
• Utilize the performance data-driven flow to drive the NPU architecture definition.
• Collaborates with management, product owners, and project managers to evaluate feasibility of requirements and determine priorities for development.
• Performs pathfinding, surveys technologies, participates in standards committees, and presents at external and internal events.
• May interact with multiple technologists in the company to influence architectures and optimize/customize software offerings.

Qualifications:

You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Qualifications could be obtained through a combination of schoolwork, classes, research, and/or relevant previous job and/or internship experiences.

Minimum Qualifications

• Bachelor's Degree in Electrical Engineering, Computer Engineering, or Computer Science or related engineering field with 6+ years of relevant experience – OR – Master's Degree in Electrical Engineering, Computer Engineering, or Computer Science or related engineering field with 4+ years of relevant experience – OR – PhD in Electrical Engineering, Computer Engineering/Computer Science with 2+ years of relevant experience, or related engineering field
• 6+ years of experience in two or more of the following:
  • Knowledge of computer architecture concepts such as pipelining, caching, parallel computing with SIMD/VLIW,multi-core/multi-threading,data precision, memory hierarchy
  • Understanding HW modeling concepts such as event-driven, concurrency, etc.
  • Knowledge of AI framework, AI models and basic neural computing operations.
  • Knowledge of data precision, floating point vs fixed point computing trade-offs.

Preferred Qualifications

• Experiences for object-oriented programming in C/C++ or Python. Capable of design class objects, data structure and API methods are required.
• Prior usage of event-driven modeling language (SC/C++/Python) and platforms
• Prior experience in architecture definition and/or mentoring junior engineers is highly desirable.

Experienced HireShift 1 (United States of America)US, California, Santa ClaraUS, Arizona, Phoenix, US, California, Folsom, US, Oregon, Hillsboro, US, Oregon, Portland
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 168,100.00 USD - 299,040.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

Responsibilities include, but are not limited to:

• Develops the logic design, register transfer level (RTL) coding, and simulation for an SoC design and integrates logic of IP blocks and subsystems into a full chip SoC or discrete component design.

• Participates in the definition of architecture and microarchitecture features of the block being designed.

• Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence.

• Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.

• Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.

• Follows secure development practices to address the security threat model and security objects within the design.

• Works with IP providers to integrate and validate IPs at the SoC level. Drives quality assurance compliance for smooth IPSoC handoff.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

This is an entry level position and will be compensated accordingly.

Minimum qualifications:

Bachelor’s degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field with 1+ years' experience withScripting (python, pearl, or other similar programming languages)

— or —

Master’s degree or PhD in the same fields

Preferred qualifications:

• UPF coding.

• Integrating and ensuring IP components within SOC

• Implementing physical connectivity

• Testing and verification

Experience would be obtained through a combination of prior education level classes, and current level school classes, projects, research and relevant previous job and/or internship experience.

College GradShift 1 (United States of America)Virtual US
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 90,890.00 USD - 170,890.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. However, you must live and work from the country specified in the job posting, in which Intel has a legal presence. Due to legal regulations, remote work from any other country is unfortunately not permitted. * Job posting details (such as work model, location or time type) are subject to change.The application window for this job posting is expected to end by 08/31/2026

Role Overview:

The Senior Thermal Architect will lead thermal design and strategy for next-generation GPU, AI accelerators, and data center products. This role is critical to enabling high-performance computing at scale while meeting stringent thermal requirements. You will define thermal architecture across silicon, package, and platform levels, ensuring optimal thermal performance for products approaching multi-kilowatt levels:

Key Responsibilities:

• Define and deliver advanced packaging thermal solutions for advanced GPU/AI products
• Architect thermal strategies for 3DIC and advanced packaging technologies, including chiplets and heterogeneous integration.

• Develop analytical and experimental methods for thermal characterization and prediction.
• Drive co-optimization of thermal, electrical, and mechanical design across silicon, package, and system levels.

• Push the boundaries of thermal management to support Moore's Law progression.
• Evaluate and integrate emerging cooling technologies (e.g., liquid cooling, immersion cooling) for data center sustainability.

• Partner with silicon design, packaging, and platform teams to ensure thermal compliance and performance.
• Engage with external customers and ecosystem partners to align thermal solutions with product requirements.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Knowledge and/or experience listed below would be obtained through a combination of your school, work and/or classes and/or research and/or relevant previous job and/or internship experiences

Minimum Qualifications

• MS or PhD in Mechanical Engineering, Thermal Sciences, or related field.
• 10+ years in thermal design of semiconductor products
• Proven track record in thermal architecture and advanced packaging.
• Proficient in thermal simulation tools (e.g., CFD, FEA) and experimental validation.

Preferred Qualifications

• 10 + years experience in high-performance computing or data center products.
• Proven track record in GPU/AI thermal architecture and advanced packaging.
• Experience with rack-scale cooling solutions and liquid cooling technologies.
• Familiarity with AI/GPU performance trends and their thermal implications.
• Strong understanding of power delivery, energy efficiency, and cooling technologies.
• Ability to influence architecture decisions and drive innovation across global teams.

Experienced HireShift 1 (United States of America)US, Arizona, PhoenixUS, Oregon, Hillsboro
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 136,990.00 USD - 262,680.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

• Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.

• Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.

• Defines SoC or subsystem level clocking targets and drives design teams to achieve these objectives as required.

• Builds simulation models, drives physical implementation, conducts clock analysis, and supports power grid methodologies and implementation.

• Creates scalable flows for clocking infrastructure for better performance and power in the design. Interacts with architecture and IP/SoC design teams to understand clocking requirements and helps them in deciding the right clock distribution methodology based on power and performance requirements.

This position offers work remotely if not co-located at the Fort Collins, CO site.

Qualifications:

Minimum Qualifications:

• Bachelor's degree in Electrical / Computer Engineering, Computer Science or in a STEM related field of study with 5+ years of relevant experience

• -OR- Master's in Electrical / Computer Engineering, Computer Science or in a STEM related field of study with 4+ years of relevant experience

Relevant experience should include the following:

• 4+ years of experience hands-on experience across the entire spectrum of RTL to GDS implementation on advance semiconductor technology nodes and specific challenges in clock design.

• 4+ years of experience in Clocking techniques, static timing analysis (STA), clock domain crossing (CDC) checks, jitter/skew analysis and low-power clocking strategies.

Preferred Qualifications:

• Experience with scripting skills in Tcl, Perl, or Python for automation and flow enhancements Understanding of signal integrity, electromigration, and power integrity in the context of clock networks.

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and orschoolwork/classes/research.

Experienced HireShift 1 (United States of America)Virtual US
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 139,710.00 USD - 262,680.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. However, you must live and work from the country specified in the job posting, in which Intel has a legal presence. Due to legal regulations, remote work from any other country is unfortunately not permitted. * Job posting details (such as work model, location or time type) are subject to change.The application window for this job posting is expected to end by 11/28/2025

Job Description:

Responsibilities include, but are not limited to:

• Performs low level and complex debug for multiple systems, subsystems within a product, or at the SoC level primarily for Intel datacenter silicon products.

• Works to continuously improve the debug discipline through new design for debug (DFD) tools and scripts.

• Applies deep understanding of SoC design, architecture, firmware, and software to resolve triage failures, marginality issues, and conduct root cause analysis.

• Defines, develops, and implements techniques for faster debug at the SoC and platform level and isolates failing components of a system.

• Drives bench test and formulates debug requirements and strategies at the system level, ensuring compatibility with architecture.

• Develops test methodologies for new device features and functionality, engages in new product debug, and improves debugging workflow and characterization activities.

• Collaborates with design, system validation teams, and high-volume manufacturing factories to track SoC debug readiness.

Qualifications:

This is an entry level position and will be compensated accordingly.

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience would be obtained through a combination of prior education level classes, and current level school classes, projects, research and relevant previous job and/or internship experience

Minimum Qualifications:

Bachelor’s degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field orMaster’s degree in the same fields

Preferred Qualifications:

• Experience with Silicon micro-architecture

• Experience with Software/programming

College GradShift 1 (United States of America)US, Massachusetts, Beaver BrookUS, Arizona, Phoenix, US, California, Santa Clara, US, Oregon, Hillsboro, US, Texas, Austin
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 90,890.00 USD - 148,080.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.