Senior Packaging Thermal Architect jobs at Intel

Job Description:

) is at the forefront of silicon photonics integration and is part ofData Center, connected computing-devicesnearly aand higher speeds from 400G today to 1.6T+ and beyond tomorrow. We are looking forgreat talentto accelerate thisso if you are interested in joining our leadingthen we want to hear from you.

The team is seeking an experienced Hardware Designer with expertise in SI and PI to support the development of reference module designs, PIC sub-system EVB and other test boards to support product development. Demonstrated expertise in designing 100G/lane and 200G/lane module PCBA, lead the layout execution for high-speed traces, power delivery, require extensive experience with designing PDN for high-speed DSP, RFICs, manage PI and SI requirements, actively guide layout engineer and manage tradeoffs in design. The candidate will be expected collaborate with a cross functional product development team - HW, FW, PIC, EIC, Packaging and thermal, Optics and NPI.

Job responsibilities include but are not limited to:

• Perform SI simulations of high-speed interfaces, RF traces, etc. 100Gbps, 200Gbps NRZ and PAM4 signaling.
• Modeling of high speed traces with vias, connectors, sockets and various system components in 3D EM tools like HFSS, ADS.
• Design and optimize Power Delivery Network (PDN) across packages and PCBs.
• Perform PI sims for IR drop, current density violations, dynamic switching noise analysis to validate board designs.
• Expertise in designing 100G/lane and 200G/lane module PCBA, lead the layout execution for high-speed traces, power delivery, require extensive experience with designing PDN for high-speed DSP, RFICs, manage PI and SI requirements, actively guide layout engineer and manage tradeoffs in design.
• Ability to lead hardware design of an optical transceiver and evaluation boards including schematic design, circuit simulation, PCB layout floor planning, design with layout engineer is a plus.
• Lead PCB bring up working with FW engineers to confirm functionality w.r.t design targets. Validate PCB high speed designs thru product design verification tests and independent PCBA characterization. Troubleshoot and optimize performance of thesub-system/transceivermodule boards.
• Extensive experience with selection of DSP, Driver, TIA, uControllers, DACs, ADCs, Voltage regulators, etc.
• Key contributor to Product Requirements, Owns PCBA design from concept phase to full final design and EVT/DVT phase of the product.
• Understand electrical and optical requirements and specifications of optical transceiver MSA. Like 800G DR8/2xFR4, 1.6T DR8/2xFR4, 800G LPO, 1.6T LRO etc.
• Maintain documentation of a hardware design specification, Pass design check list prior to tape out, BOM specifications and work with NPI team to build PCBA. Lead design reviews and present design summary to management, highlight risks with mitigation plans.
• Interface and work collaboratively with mechanical engineers, optical engineers, Photonics engineer, firmware engineers, process engineers and test engineers.
• Interact with program manager, buyer/planner and suppliers to make sure designed parts are available in a timely manner for build and test.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

• M.S. in Electrical Engineering
• 4+ years of HW/circuit design experience
• 4+ years of experience in:
  • transceiver electrical design principles, including high speed signal integrity, crosstalk, power integrity, noise, ESD, FW, testing, etc.
  • layout and able to direct layout engineer with clear design priority
  • PI and SI tools (HFSS, ADS, Cadence)
  • high density multiple-layer board design.
  • high volume PCB/substrate fab houses.

Preferred Qualifications

• Ph.D. in Electrical Engineering
• Strong analog and digital circuit design skills and layout with mixed signal designs.
• Experience working with AWG, DCAM, VNA/LCA to characterize high speed performance
• Strong laboratory optical and electrical measurement skills.
• Strong communication and presentation skills.
• Experience with micro-controllers and communication protocols such as SPI, I2C, MDIO, CMIS management interface for optical modules.
• Strong background of digital communication theory.
• Familiarity with industry standards including IEEE Ethernet standards, OIF standards, PCIe standards and various MSAs.
• Experience with optical transceiver test and calibration methodologies.
• Experience working with Marvell, Broadcom, MaxLinear, Credo DSPs in pluggable optical modules.

Experienced HireShift 1 (United States of America)US, California, Santa ClaraUS, Arizona, Phoenix
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 161,230.00 USD - 303,140.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

Since pioneering the world’s first hybrid silicon laser, IPS has led the industry in scalable, high-volumemanufacturing andadvanced photonics development. Our mission: deliver next-generation bandwidth growth with smaller form factors, co-packaging, and speeds from 400G today to 1.6T+ tomorrow.

We are seeking a Lead Analog SerDes Architect / Design Engineer to join our team and shape the future of data center connectivity. In this role, you will:

• Defining circuit architecture and enabling designs meeting power, and performance for next generation optical interconnects based on system specifications.
• As part of the team developing key integrated circuit components the engineer must be able to work collaboratively leading block level development.
• Specify, architect and design low voltage and low power Mixed-Signal integrated circuits and work collaboratively with digital designers.
• Plan design work with constraints on performance, schedule and quality.
• Provide guidance to junior designers and layout engineers.
• Guidance to develop test plans for post-silicon characterization.
• Document all design work with review materials and detailed design descriptions.

Minimum QualificationsThe ideal candidate should have a minimum of MS in Electrical Engineering with 8+ years of experience in high-speed serial links and deep knowledge of analog CMOS/BiCMOS designs in deep sub-micron process technologies.• Hands-on circuit design experience of SerDes blocks like Equalizers, PLL, Phase-Interpolators, CDR, etc. for 28Gbps+ data rates.
• Experience with design of inductors, transmission line, Trans-Impedance Amplifiers (TIA) and modulator drivers.
• Experience with design of precision analog circuits like ADC/DACs.
• Experience with designing PAM4/NRZ links.
• Experience with Mixed signal design flow
• Experience with full-chip designs, ESDs and verification flows.
Preferred Qualifications
• Familiarity with Optical communications.
• Experience with 400G/800G/1.6T optical links.
• Experience with package/test setup design.

Experienced HireShift 1 (United States of America)US, California, Santa Clara
Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 214,730.00 USD - 303,140.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

We are seeking a Senior Device Engineer to drive the development of next-generation CMOS device technologies in our high-volume manufacturing environment. You will collaborate with cross-functional teams to develop innovative semiconductor solutions, optimize manufacturing processes, and deliver customized device architectures that meet our foundry customers' most demanding requirements.

Key Responsibilities

Data Analysis and Optimization: Utilize advanced data analysis, scripting, and analytical techniques to accelerate learning and drive continuous improvement. Interpret complex product data including inline, e-test, and SORT data to identify failure root causes and develop effective solutions.

Adaptability andProblem-Solving -Navigating changing technology landscapes while troubleshooting complex issues under tight timelines.

Qualifications:

Bachelor's Degree in Electrical Engineering, Physics, or related field with 7+ years of experience in CMOS device engineering, device physics, logic architecture, and interconnect development on leading-edge technology nodes.

The experience must include:

• Advanced CMOS device technology, preferably in a foundry environment.
• Foundry NPI. Device targeting and corner skew.
• IC wafer fabrication process engineering, manufacturing systems, semiconductor materials, and wafer testing across various fabrication areas including photolithography, advanced patterning, thin film deposition, planarization, defect metrology, and spectroscopy.
• Interpreting product data including inline, e-test, and SORT data, finding failure root cause and inline indicators, and driving for solutions.

Preferred Qualifications

• Post-graduate degree in Electrical Engineering, Physics, or related field with 6+ years of specialized CMOS device engineering experience.
• Direct hands-on experience in advanced node semiconductor technology development, particularly with 3nm-16nm FinFETs and sub-3nm GAA FETs.
• Experience in high-volume manufacturing environments with proven ability to balance foundry and customer needs.
• Expertise in Process Design Kit (PDK) silicon model target generation,silicon-to-simulationcorrelation, test structure design, device modeling, and electrical characterization.
• Direct customer-facing experience with familiarity in industry standards and certifications.

Experienced HireShift 1 (United States of America)US, Arizona, PhoenixUS, Oregon, Hillsboro
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 117,140.00 USD - 226,150.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

In this position, you will function as a senior technical member in the NPU architecture performance COE(center-of-excellence)

The role’s responsibilities include but are not limited to:

• Define performance model architecture and modeling flow to best reflect the interworking of NPU SW/HW.
• Implementing and testing performance models with systematic SW development practice.
• Conductperformance-and-poweranalysis of various neural network workloads.
• Utilize the performance data-driven flow to drive the NPU architecture definition.
• Collaborates with management, product owners, and project managers to evaluate feasibility of requirements and determine priorities for development.
• Performs pathfinding, surveys technologies, participates in standards committees, and presents at external and internal events.
• May interact with multiple technologists in the company to influence architectures and optimize/customize software offerings.

Qualifications:

You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Qualifications could be obtained through a combination of schoolwork, classes, research, and/or relevant previous job and/or internship experiences.

Minimum Qualifications

• Bachelor's Degree in Electrical Engineering, Computer Engineering, or Computer Science or related engineering field with 6+ years of relevant experience – OR – Master's Degree in Electrical Engineering, Computer Engineering, or Computer Science or related engineering field with 4+ years of relevant experience – OR – PhD in Electrical Engineering, Computer Engineering/Computer Science with 2+ years of relevant experience, or related engineering field
• 6+ years of experience in two or more of the following:
  • Knowledge of computer architecture concepts such as pipelining, caching, parallel computing with SIMD/VLIW,multi-core/multi-threading,data precision, memory hierarchy
  • Understanding HW modeling concepts such as event-driven, concurrency, etc.
  • Knowledge of AI framework, AI models and basic neural computing operations.
  • Knowledge of data precision, floating point vs fixed point computing trade-offs.

Preferred Qualifications

• Experiences for object-oriented programming in C/C++ or Python. Capable of design class objects, data structure and API methods are required.
• Prior usage of event-driven modeling language (SC/C++/Python) and platforms
• Prior experience in architecture definition and/or mentoring junior engineers is highly desirable.

Experienced HireShift 1 (United States of America)US, California, Santa ClaraUS, Arizona, Phoenix, US, California, Folsom, US, Oregon, Hillsboro, US, Oregon, Portland
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 168,100.00 USD - 299,040.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

Job Description:

• Develop and validate finite element analysis (FEA) models to simulate thermal and mechanical behavior of advanced semiconductor packages. Perform simulations to evaluate stress, strain, warpage, delamination, thermal cycling, and reliability risks across a wide range of package architectures.

• Collaborate with cross-functional teams to define simulation requirements, interpret results, and provide actionable design and process recommendations. Design and coordinate lab tests and research on basic materials and properties to understand material behavior and reliability failure mechanisms.

• The ideal candidate will have to drive strategic development activities and work closely with internal and external customer organizations to plan, execute and communicate development activities and programs.

• The team leverages both experimental and numerical methods across a broad range of areas, including thermal, mechanical, and fluids.

• The team typically uses a combination of simulations and experiments, as needed, to help solve practical engineering problems.

• The team frequently leverages advanced analysis methods (statistical, AI/ML) to supplement modeling and experimental approaches.

Note:This role requires regular onsite presence to fulfill essential job responsibilities. Provides tactical and strategic operational support to ensure the successful development and ramp of a high volume or technology development fabrication facility.

The ideal candidate should exhibit the following skills or behavioral traits:

• Demonstrated ability to work seamlessly between experiments and simulations.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and orschoolwork/classes/research.

Minimum Qualifications:

• Master's Degree in Mechanical Engineering, Chemical Engineering or Material Sciences or a related field with emphasis in solid mechanics and 3+ years of relevant experience
• -OR- PhD Degree in Mechanical Engineering, Chemical Engineering or Material Sciences or a related fieldwith emphasis in solid mechanics

Experienced HireShift 1 (United States of America)US, Arizona, PhoenixUS, Oregon, Hillsboro
Position of Trust

offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 100,160.00 USD - 193,390.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

We are seeking an experienced NPI Transfer Manager to lead new product introduction and technology transfer initiatives from concept through production qualification. This role serves as the primary interface between ourAdvanced Packaging Technology and Development
Key Responsibilities
1. NPI Leadership and Execution

• Lead comprehensive New Product Introduction (NPI) and technology introduction processes from early engagement planning through sample generation, Product Release Qualification (PRQ), and transfer certification
• Demonstrate strong leadership capabilities to drive teams forward during ambiguous situations, resolve competing priorities, and logically balance NPI loading across the network with high product and technology variation
• Formalize business processes to facilitate resource mobilization and close competency gaps, achieving both efficiency and effectiveness across operations and product/package platforms

2. Cross-Functional Collaboration

• Foster strategic collaboration with Division teams, Technology Development, and supply chain organizations that contribute to transfer success
• Partner with Technology Development (TD), Factory NPI teams, and all partners to drive solutions from NPI through End of Life (EOL)
• Collaborate with factory NPI team and TD key players to track and resolve all technical issues during NPI transfer

3. Customer Interface and Relationship Management

• Serve as the main interface to customers (e.g. CCG, DCG) and customer-facing teams (e.g. PBG), acting as the Voice of the Customer to APTM NPI operations
• Develop in-depth understanding of customer needs across various business units (CCG, DCG, NEX, PSG, FS) leveraging Foundry Services Expertise and OSAT benchmark knowledge
• Represent APTM NPI in customer Quarterly Business Reviews (QBRs) or Quarterly Technical Review (QTRs), site visits, audits, and aligned customer operational metrics reviews
• Lead NRE (Non-Recurring Engineering) and SOW (Statement of Work) engagements on behalf of APTM NPI

4. Technical Support and Problem Resolution

• Provide comprehensive technical support to resolve NPI and High Volume Manufacturing (HVM) issues
• Track and close all technical opens in collaboration with cross-functional teams
• Partner with TD to drive technology readiness and represent HVM-friendly voice in technology affordability initiatives

Required Experience

• Proven experience in NPI management and product transfer processes
• Strong background in semiconductor manufacturing, and backend operations e.g. assembly, and test operations
• Demonstrated ability to manage complex, multi-stakeholder projects
• Excellent communication and presentation skills for customer-facing responsibilities
• Experience with foundry operations and customer relationship management

Preferred Experience

• Experience with various customer segments
• Proven record in managing NPI department and Transfer Programs

Key Competencies

• Strategic thinking and problem-solving abilities
• Strong leadership and team management skills
• Customer relationship management
• Cross-functional collaboration
• Technical expertise in manufacturing processes
• Ability to work effectively in ambiguous and fast-paced environments

Qualifications:

• Bachelor's degree in Engineering, Manufacturing, or related technical field
• 10 years of experience in NPI management and product transfer processes

Experienced HireShift 1 (United States of America)US, New Mexico, Albuquerque
Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 187,330.00 USD - 264,470.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

• Develop and validate detailed finite element analysis (FEA) models to simulate thermal and mechanical behavior of advanced semiconductor packages. Perform simulations to evaluate stress, strain, warpage, thermal cycling, and reliability risks across a wide range of package architectures.

• Collaborate with cross-functional teams to define simulation requirements, interpret results, and provide actionable design and process recommendations. Design and coordinate lab tests and research on materials and properties to understand material behavior and reliability failure mechanisms.

• Support technology roadmap development by evaluating new materials, interconnect structures, and process flows from a thermo-mechanical reliability perspective.

• Drive design-of-experiment studies and sensitivity analyses to understand key drivers of package performance and reliability

• Contribute to the development and automation of internal simulation workflows, tools, and best practices to improve modeling efficiency and accuracy

• Develop solutions to problems utilizing formal education, experience and engineering judgment

• Communicate recommendation and solution space to internal and external customers. Responds to customer/client requests or events as they occur.

• Document and present simulation methodologies, results, and recommendations to both technical and executive audiences

• Stay current with industry trends, emerging technologies, and academic research in advanced packaging and simulation methodologies

• Strong communication skills across internal and external stakeholders andplanning/prioritizationskills for project success

• Ability to handle ambiguity and use appropriate skills (behavioral and/or technical) to drive clarity across stakeholders

• Willingness to lead and influence both external and internal teams

• Willingness to work independently with minimal supervision

• Technical problem-solving skills in a highly dynamic team environment

This role requires regular onsite presence to fulfill essential job responsibilities. Provides tactical and strategic operational support to ensure the successful development and ramp of a high volume or technology development fabrication facility.

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.Minimum Qualifications:

• Master's Degree in Mechanical Engineering, Chemical Engineering, Material Sciences or a related field and 7+ years of industry experience

• -OR- PhD Degree in Mechanical Engineering, Chemical Engineering, Material Sciences or a related field and 4+ years of industry experience

Industry experience should include the following:

• Thermo-mechanical FEA modeling in semiconductor packaging domain

• At least one of the commercial FEA tools such as ANSYS, ABAQUS and COMSOL

• Advanced packaging technologies such as Foveros, EmIB, Cowos and Hybrid bonding.

• Semiconductor packaging processes, including die attach, underfill, molding, bumping, surface mount and reflow.

Preferred Qualifications:

• Experience with multi-physics simulations, including coupledelectro-thermal-mechanicalanalysis, free surface two phase flows, electroplating and plasma

• Familiarity with JEDEC reliability standards and qualification tests

• Experience with scripting and automation (e.g., Python, TCL, MATLAB) to streamline simulation workflows

• Experience in technical program management in any assembly or test functional area

• Experience in driving yield improvement activities for advanced package architectures

• Previous related work experience in asemiconductor foundry preferred

Experienced HireShift 1 (United States of America)US, Arizona, PhoenixUS, Oregon, Hillsboro
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 136,990.00 USD - 264,470.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.