Intel Government Technologies Product Architect jobs at Intel

Job Description:

About the Role: We are seeking a highly experienced Senior Software Expert specializing in SoC Power and Performance Architecture to join our innovative team. In this pivotal role, you will leverage your expertise to enhance the power efficiency and performance of our System-on-Chip (SoC) designs. You will collaborate with cross-functional teams to ensure our SoCs achieve optimal performance and power efficiency, while identifying and implementing opportunities for improvement. You will also be setting simulation methodologies and driving those across the teams.

Key Responsibilities:
• Power and Performance Optimization: Lead and drive initiatives to optimize SoC power and performance through advanced software techniques, including firmware tuning, workload analysis, and architectural design modifications.
• Collaboration: Partner with architects, design engineers, validation teams, and marketing to deliver industry-leading SoC solutions, providing software insights and expertise.
• Pre-Silicon Planning: Define and implement detailed power and performance tools and methodologies in the pre-silicon phase, focusing on software architecture and design.
• DevOps Pipeline Establishment: Develop and establish DevOps pipelines for power, performance, and thermal architecture tools and methodologies, ensuring efficient and automated workflows.
• Simulation Technologies: Establish and implement simulation technologies and methodologies to predict and analyze power, performance, and thermal characteristics.
• Simulation Model Development: Develop and refine simulation models for power, performance, and thermal analysis, enabling accurate and predictive assessments of SoC designs.

Qualifications:

Minimum Qualifications:

• Bachelor's degree with 7+ years of experience or
• Master's degree with 5+ years of experience, or
• PhD with 2+ years of experience in Electrical Engineering, Computer Engineering, or a related field.

Preferred Qualifications:

• In-depth knowledge of CPU architecture, benchmarks, power management, and memory sub-system validation.
• Extensive experience in simulation development in the pre-RTL phase.
• Strong background in SW architecture and quality.
• Proficiency in developing simulation models for SoC.
• Advanced software development skills, including experience with scripting languages such as Python, C++.
• Deep understanding and experience with operating systems.
• Expertise in statistical data analysis and design of experiments.
• Familiarity with industry benchmarks, understanding the aspects of performance they measure, and conducting competitive analysis from previous generation products.

Experienced HireShift 1 (United States of America)US, Oregon, HillsboroUS, Arizona, Phoenix, US, California, Folsom, US, California, Santa Clara
Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

Key Responsibilities

• Architectural Leadership: Lead the architectural definition and integration of high-speed PHYs for client SoCs, including PCIe, CXL, USBx (e.g., eUSB2, USB3, USB4), Display, MIPI (D-PHY, C-PHY, M-PHY), Ethernet, and TSN. Collaborate with platform and product architects to analyze requirements and define critical performance, power, and area specifications to ensure the success of our products.
• IP Evaluation: Conduct technical evaluations of both internal and external PHY IPs, analyzing their performance characteristics against product requirements, and ensuring strategic alignment with overall product goals. Define detailed IP requirements, lead vendor engagement, and make strategic IP selection recommendations based on technical feasibility, cost-effectiveness, and long-term roadmap alignment.
• Technology Vision: Proactively research and evaluate emerging high-speed I/O technologies, industry trends, and evolving standards. Identify and champion opportunities to incorporate these advancements into our product roadmap, enhancing performance, power efficiency, and feature sets, and positioning our products for competitive advantage.
• Technical Documentation: Create clear and comprehensive architecture specifications and rigorous integration guidelines. Provide review and constructive feedback on related architectural specifications to ensure alignment with overall SoC goals.
• Technical Mentorship and Collaboration: Provide technical guidance and mentoring to junior engineers, fostering their growth and contributing to the overall team expertise. Champion a collaborative environment across multiple teams.
• Post-Silicon Leadership: Serve as a technical lead in the post-silicon debug and validation of high-speed I/O interfaces, leading taskforces and driving the resolution of complex issues. Oversee the validation process to ensure seamless and high-quality implementations.

Additional Skills:

• Demonstrated strategic acumen with proven effectiveness in collaborating with senior technologists and business leaders across organizational boundaries.• Demonstrated ability to network with and influence a broad range of stakeholders

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications:•

• BS degree in Electrical/Computer Engineering with a minimum of 15 years of experience.
• Master's or PhD degree in Electrical/Computer Engineering with minimum 12 years of experience
  

Preferred Qualifications:

• High familiarity with industry trends within the HSIO domain and the ability to map them to Intel roadmap/products and segment strategies.
• We look forward to welcoming a dynamic and innovative High-Speed I/O (PHY) Architect to our team. Apply now and be a part of shaping the future of our client SoC technology.
• Prior hands-on experience in High-Speed IO PHY Architecture and Design.
• Strong knowledge in the interoperability of HSIO PHYs within the PCIe, SATA, Ethernet, USB2, USB3, USB4, Display or MIPI IO Controller subsystems
• Strong technical leadership and communication skills

Experienced HireShift 1 (United States of America)US, California, FolsomUS, Arizona, Phoenix, US, California, Santa Clara, US, Oregon, Hillsboro
Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

Your responsibilities may include but not be limited to:

• Define SoC fabrics, SoC hardware/software interface, and IP integration.

• Author high-level architecture specifications that meet product/market requirements and facilitate correct implementation by development teams

• Interact with Micro Architects, IP Architects, discrete GFX team, RTL Design teams, Verification teams, Emulation team, Power and Performance validation teams to understand the product requirements and define overall Display strategy to ensure the end product meets the PnP goals at pre-silicon estimation and post-silicon measurement.

• Interact withapplication/driver/firmware

The SOC Architect should possess the following attributes:

• Excellent written and verbal communication skills.

• Willingness to work effectively in a collaborative, cross-functional environment.

• Excellent problem-solving and debugging skills.

• Willingness to lead task forces to resolve problems.

Qualifications:

Bachelor's degree in Computer Science, Computer Engineering, or Electrical Engineering with:

• BS degree with 8+ years of industry experience

• OR- Master's degree with 6+ years of industry experience

• OR- PhD degree with 4+ years of industry experience

Candidate must have combined 4+ years of experience in the following areas:

• System-on-Chip (SoC) integration,

• SoC architecture,

• SoC design,

• System architecture ( such as Hardware / Software interface, PNP )

Preferred Qualifications:

• IP integration and SoC flows with IP's such as Graphics, Media, or Image Processing.

• Broad knowledge of computer systems (software, hardware, firmware, silicon).

• Experience with hardware/software interfaces.

• Power and Performance.

• Experience with at least one of the following: Memory controllers, cache hierarchy, fabrics, high speed I/O protocols.

Experienced HireShift 1 (United States of America)US, Oregon, HillsboroUS, California, Folsom, US, California, Santa Clara
Position of Trust

offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

Responsibilities include:

• Develops complex code with C++ templates for optimal GPU kernels.
• Understand PyTorch or Similar framework’s usage of AI kernels and design the interfaces.
• Interacts with partner teams to understand the requirements and convert to tangible action items for development.
• Develop architectural documents for setting direction to larger team.

Behavioral traits that we are looking for:

• Excellent written and oral communication skills including technical details and concepts.
• Willingness to lead large teams of engineers with clear direction of complex requirements.
• Willingness adhering to specific timelines and delivering quality SW products.

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and orschoolwork/classes/research.

Minimum Qualifications:

• Bachelor’s degree and 6+ years or Master’s degree and 4+ years’ experience or Ph.D and 2+ years of experience in Computer Engineering, Computer Science, Data Science, Software Engineering, Electronic Engineering, Physics, Mathematics, Aerospace engineering, applied mathematics, mechanical engineering, or related technical disciplines.
• 3+ years of experience in complex C++ template-based development such as meta level programming.
• 2+ years’ experience with GPU architecture.
• 2+ years’ experience SYCL / CUDA knowledge.
• 1+ years’ experience with GEMM kernels.

How to stand out from other candidates (Preferred Qualifications):

• AI kernel developments (such as flash attention, MoE),
• Understanding of overall AI SW stack,
• Understanding of PyTorch architecture.

Our total rewards package goes above and beyond just a paycheck. Whether you're looking to build your career, improve your health, or protect your wealth, we offer generous benefits to help you achieve your goals. Go to

Experienced HireShift 1 (United States of America)US, Oregon, HillsboroUS, California, Santa Clara
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

The Datacenter Power and Performance Architecture group architects products that deliver leadership performance, performance efficiency and security for traditional as well as new paradigms for data centric computing in the datacenter and edge with the right balance of leadership technologies and IPs for computing, interconnect, memory and quality delivered through the best mix of silicon, packaging and platform solutions.

You Are

As a SOC Performance Architect responsibilities will include but are not limited to:

• You will work in a dynamic team environment hand in hand with our design, validation, and architecture teams to deliver best-in-class performance and innovations across the XEON CPU and AI portfolio.

• Determining, specifying and evaluating the viability of complex hardware features and structures and ensures that software and hardware designs interface correctly. Designs framework for particular functions.

• Defines, documents and tests processes for inclusion into technical platforms, subsystem specifications, input/output and working parameters for hardware and/or software compatibility.

• Identifies, analyzes and resolves subsystem and/or SoC design weaknesses.

• Influences the shaping of future products by significantly contributing to the architecture used across design families.

Qualifications:

You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

• Bachelor's Degree in Electrical/Computer Engineering or Computer Science with 1+ years of experience -OR- Master's Degree in Electrical/Computer Engineering or Computer Science -OR- PhD in Electrical/Computer Engineering or Computer Science.

Preferred qualifications

• Experience in in Computer architecture.

• Experience in C, C++ or Python.

• Experience in Verilog, System/Verilog.

• Experience in CPU architecture, performance and power architecture, modelling, pre and post silicon analysis.

Experienced HireShift 1 (United States of America)US, Oregon, HillsboroUS, California, Santa Clara, US, Texas, Austin
Position of Trust

offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

Job Description:

As a Senior Principal Engineer, you will architect and develop embedded software that directly interfaces with hardware components, including microcode, IP-specific firmware, FPGAs, and DSPs. You will play a critical role in defining the firmware architecture, partitioning functionality between hardware and software, and driving co-validation strategies. This role requires deep technical expertise, strategic vision, and the ability to influence cross-functional teams across silicon, platform, and software domains.

Key Responsibilities:

• Firmware Architecture & Development
  • Design and implement embedded firmware with direct hardware interaction.
  • Define and partition features and algorithms between firmware and hardware for optimal performance, power, and scalability.
• Silicon & Platform Collaboration
  • Collaborate with silicon architects to define hardware requirements and influence architectural decisions.
  • Drive co-validation strategies across hardware and firmware to ensure seamless integration and functionality.
• Innovation & Pathfinding
  • Lead pathfinding efforts to explore emerging technologies and architectures.
  • Provide technical recommendations that shape future silicon and platform designs.
• Methodology & Process Improvement
  • Develop and refine methodologies, models, and tools to enhance firmware development and validation efficiency.
  • Champion best practices in embedded systems design and continuous improvement.
• Technical Leadership & Mentorship
  • Act as a domain expert and thought leader across the organization and industry.
  • Mentor and develop technical talent, fostering a culture of innovation and excellence.
  • Align organizational goals with technical strategy and drive execution from concept to product delivery.

Minimum Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.
• 10+ years as firmware architect/lead for either a data center product or technology

Preferred Qualifications:

• Technical mastery in at least 1-2 technical areas of a typical data center products
• Experience with defining (new) interfaces for multiple FW ingredients and microcontrollers

Experienced HireShift 1 (United States of America)US, Texas, Austin
Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

Job Description:

This position will report to the Vice President U.S. Government Affairs and will be located in our Washington, DC office. This position will manage outreach to the Executive Branch and Congressional Republicans to advocate and shape policies that advance American semiconductor manufacturing and technology leadership.

• Create and execute federal lobbying efforts that advance our policy positions and achieve favorable outcomes, with a particular focus on manufacturing and trade:

• Advocate for Intel's positions on critical policy issues at a time of dynamic change for the semiconductor industry.

• Articulate a clear, compelling vision for the importance of U.S. domestic semiconductor manufacturing, Intel's leadership role in the industry, and the federal policies needed to support these priorities.

• Lead lobbying efforts on export controls (Executive Branch), investment restrictions, and critical minerals.

• Work with the U.S. Government Relations team to develop and execute Intel's strategic and tactical responses to pending legislation, regulation, and policy issues, including internal alignment and external engagement with trade associations, relevant third parties, and directly with policymakers.

• Build strong relationships with key policymakers and other federal authorities to enhance Intel's reputation and influence with the federal government.

Qualifications:

• At least 7+years of relevant experience with the U.S. federal government; focusing on manufacturing policy, but with ability to work across a broad portfolio of issues

• Past experience of lobbying elected officials, policymakers, government agency heads, and trade associations at a government affairs position in industry or other relevant position

• Bachelor's degree required. Advanced degree (e.g., JD, MBA, MPA, MPP) is highly desirable.

• Proven track record of understanding and influencing legislative processes, including successful advocacy efforts that achieved favorable policy outcomes

• Broad government relations/policy understanding (internal and external)

• Clear reputation for ethical conduct and unquestionable integrity

• Excellent political and business judgment; high degree of discretion; strong analytical skills

• Exceptional verbal and written communication skills

College GradShift 1 (United States of America)US, Washington, D.C.
Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: