Director Product Management Silicon Photonics jobs at Intel

Strategic Planning & Development

• Design and manage end-to-end customer samples plans and activities for specific products or product groups

• Develop, document, and implement standardized sampling procedures and methodologies

• Identify and establish critical quality control checkpoints throughout sampling processes

Stakeholder Management & Communication

• Act as primary interface with internal stakeholders and leadership across all project phases

• Participate in management review committees and strategic decision forums

• Own all customer communications related to sampling programs

Cross-Functional Coordination

• Manage interdependencies and communicate sampling plans to business partners

• Collaborate with Product Development Teams (PDTs) and Management Review Committees (MRCs)

• Coordinate with quality assurance teams to ensure sampling integrity

Data-Driven Decision Making

• Apply advanced data analytics and business intelligence to optimize sample allocation

• Make complex allocation decisions balancing division priorities with constrained supply

• Utilize experiential data to improve sampling efficiency and customer satisfaction

• Assess program risks and develop mitigation strategies to meet timeline and quality objectives

Behavioral Traits

• Strong analytical and problem-solving skills

• Excellent communication and stakeholder management capabilities

Minimum Qualifications

• Bachelor's Degree in Supply Chain Management or similar field

• 4+ years of relevant experience in supply chain, product planning, or related field

• Experience with manufacturing processes, supply chain management

Preferred Qualifications

• Experience with Power BI dashboarding and advanced Microsoft Excel functionality

• Experience with Intel-specific tools including:

  • My Samples

  • SPEED/IDET

  • ISM (Intel Sample Management)

• Data analytics and business intelligence experience

• Experience in semiconductor or technology supply chain management

• Project management certification or experience

Experienced HireShift 1 (United States of America)US, Oregon, Hillsboro
Position of Trust

offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

Job Description:

This role fills these responsibilities:

Cultivate customer engagement: Enable customer first technical engagement to ensure Intel products deliver features, requirements, and execution to delight our customers.

Ensure compliance: Oversee program performance against regulatory and internal standards and ensure timely reporting and review.

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

• MS degree in Computer Engineering, Computer Science, Electrical Engineering, or equivalent.
• 15+ years' experience in computer silicon architecture, security, or related roles;
• 8+ years in senior leadership positions managing global teams and operational programs

Preferred Qualifications:

• Familiarity security and privacy technologies and standards
• Understanding of Security Development Lifecycles (SDL)
• Knowledge of computer architecture (CPU, SoC, chipsets, BIOS, Firmware, Drivers, and others)
• Working knowledge of hardware or software architecture and design
• Strong communication and influence skills to inform and influence a variety of internal and external audiences including customers, architects, managers, and developers

Experienced HireShift 1 (United States of America)US, California, FolsomUS, Arizona, Phoenix, US, California, Santa Clara, US, Oregon, Hillsboro
Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

• Lead and manage a team of silicon physical design engineers responsible for end-to-end silicon design engineering activities supporting technology development, and product design execution on EMIB 2.5D/3.5D, Foveros S/R/B, and Foveros Direct 3D Intel foundry advanced packaging technologies.

• Oversee planning, scheduling, and execution of design projects, ensuring milestones and deadlines are met.

• Drive continuous improvement in design methodologies, flows, and processes to enhance quality and efficiency.

• Collaborate with cross-functional teams (technology partners, packaging, analysis, and verification) to ensure seamless integration and manufacturability.

• Provide technical leadership and mentorship, fostering a culture of innovation and accountability.

• Responsible for enabling teams to execute through clear goal setting, facilitating work, maintaining accountability, applying differentiated performance management, and driving team results.

• Drives results by inspiring people, role modeling Intel values, developing the capabilities of others, and ensuring a productive work environment.

Key Responsibilities:

Leadership and Management

• Lead and manage a group of Silicon Packaging Engineers, providing guidance, mentorship, and support to ensure the successful execution of projects.

• Oversee the planning, scheduling, and execution of package design projects, ensuring that milestones and deadlines are met.

• Foster a collaborative and innovative team environment, encouraging continuous learning and professional development.

• Lead design groups, coordinating efforts across multiple teams to achieve project goals.

Technical Expertise

• Serve as the technical lead for the package design team cross multiple products.

• Drive the development of advanced packaging designs, ensuring compliance with industry standards and best practices.

• Collaborate with cross-functional teams, including package architects, silicon and board design teams, design rule owners, electrical analysis engineers, and integration teams to define and implement design specifications.

• Leverage extensive experience in advanced packaging designs to meet design KPIs.

• Influence.

• Ensure products are designed and developed with high quality standards by overseeing design processes, risk management, and compliance throughout the product design lifecycle, working closely with cross-functional teams to identify and address potential quality issues before they arise.

Project Management

• Develop and maintain detailed project plans, including resource allocation, risk management, and progress tracking.

• Coordinate with stakeholders to ensure alignment on project goals, deliverables, and timelines.

• Conduct regular project reviews and provide status updates to senior management.

Innovation and Improvement

• Identify and implement process improvements to enhance the efficiency and quality of package designs and development.

• Stay current with industry trends and emerging technologies, incorporating new methodologies and tools into the design process.

• Drive innovation in product design, exploring new approaches and techniques to achieve competitive advantages.

The ideal candidate should exhibit the following behavioral traits:

• Excellent leadership and team management skills, with the ability to inspire and motivate a diverse team of engineers.

• Strong project management skills, with the ability to manage multiple projects simultaneously and meet deadlines.

• Exceptional problem-solving and analytical skills, with a keen attention to detail.

• Excellent communication and interpersonal skills, with the ability to collaborate effectively with cross-functional teams and stakeholders.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

• Bachelor's degree in Electrical Engineeringor STEM related field with 9+years of relevant experience

• -OR- Master's degree in Electrical Engineeringor STEM related fieldwith 6+ years ofrelevant experience

• -OR- PhD in Electrical Engineeringor STEM related fieldwith 4+ years of relevant experience

Relevant experience should include the following:

• Experience in silicon design, with at least 3 years in a leadership role.

• Proven experience in a leadership or management role, with a track record of successfully leading engineering teams and delivering complex projects withinestablished timelines.

• Experience with design flows and methodologies (physical design, verification).

• Experience working with EDA tools from Cadence, Synopsys, and/or Siemens.

Preferred Qualifications:

• Experience with advanced nodes and packaging technologies

• Experience in RTL2GDS flows and methodologies

Experienced HireShift 1 (United States of America)US, Arizona, PhoenixUS, Oregon, Hillsboro
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

This role's responsibilities include but are not limited to:

• Supports the deployment of human resources software solutions for the human capital management initiatives of the organization, while partnering with Human Resources and business partners to ensure success.
• Serves as technical liaison and assist specialists in the design and integration of policies, systems procedures, databases, software.
• Develops, modifies, and supports human resources automation and provides timely and accurate updates to Human Resources Management Systems (HRMS).
• Manages permissions, access, personalization, and similar system operations and settings for users.
• Provides support in administration, configuration, maintenance, and optimization of enterprise level applications that support operations.
• Audits, updates, verifies, and maintains associated data in HRMS, including promotions, adjustments, new hire approvals, rehires and data corrections for periodic reports of employee record data.
• Performs system maintenance, including assisting in the review, testing and implementation of HRMS upgrades or patches.
• Reviews and conducts regularly scheduled audits and updates of human resources data ensuring that information provided on various human resources data forms is consistent with HRMS standards to ensure data integrity.
• Participates in system testing relative to patches, fixes,upgrades/conversions,or new module implementations.
• Develops strong relationships with customers to understand business processes and identify value drivers.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. This position is not eligible for Intel immigration sponsorship.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Computer Engineering, System Engineering or related field, or equivalent experience in lieu of a degree.
• 1+ years of experience in the following:
  • Workday configuration
  • MS Excel, in particular with data validation, pivot tables, VLOOKUP's, etc.

Preferred Qualifications:

• Experience with SaaS Solutions design and configuration on Payroll and/or Recruiting module.

Shift 1 (United States of America)US, California, FolsomUS, Arizona, Phoenix, US, Oregon, Hillsboro
Position of Trust

offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

Key Responsibilities:

• Lead the co-design of silicon and package, focusing on DDR PHY and mixed signal IP integration for server SOCs.
• Design bump maps, floor plans, and manage area constraints for PHYs, collaborating closely with packaging technical experts.
• Conduct hands-onpackage extractionsand simulations(signal integrity, power integrity)
• Finalize bump-out, floor plan, and area decisions at the end of tech readiness phases.
• Interface with packaging teams on advanced technologies (e.g., C4 bumps, micro bumps, EMIB, hybrid bonding as needed).
• Focus on design, development, and architecture, not process or materials engineering.

Required Experience:

• Experience in both silicon design (preferably mixed signal/analog) and packaging co-design.
• Background in DDR, SOC, or similar high-speed interface development.
• Hands-on expertise with bump mapping, floor planning, and packaging constraints.
• Proven ability to collaborate across silicon and packaging teams, including risk assessment and simulation.
• Familiarity with advanced packaging technologies (hybrid bonding, EMIB, etc.) is a plus but not required.
• Individual contributor or principal engineer level preferred; management experience is not required.
• Experience at leading companies in advanced packaging and PHY design (e.g., Apple, Broadcom, Qualcomm, Micron, AMD, Nvidia).

Qualifications:

• Bachelors in electrical engineering, chemical engineering, mechanical engineering, material science or similar field (Master’s or Ph.D. preferred).
• 10+ years in silicon and packaging co-design

Experienced HireShift 1 (United States of America)US, California, FolsomUS, Arizona, Phoenix, US, California, Santa Clara, US, Oregon, Hillsboro
Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

Job Description:

Key responsibilities will fall into several categories:

• Tax accounting - Lead and mentor the tax team in completing the global ASC 740 tax provision process from planning and forecasting through to calculations, recording, analysis and reporting. Also drive continuous process improvements to streamline the global tax accounting process. Oversee controls and ensure processes, documentation and related systems are in compliance with Sarbanes Oxley requirements.

• US income tax reporting - manage the team to deliver all US income tax reporting including federal, state and US international tax returns. Partner with outsource compliance partner to improve standardization and automation in the US tax compliance process. Enhance documentation and drive collaboration between the tax accounting and tax reporting processes.

• Audits and Controversy - Oversee global tax audits and controversy, coordinating responses with internal stakeholders and external advisors, ensuring accurate documentation, effective risk management, and consistency across audit processes and positions.

• Value-add projects - Lead and manage delivery of high value add projects including R and D credits (R and D) and semiconductor advanced manufacturing investment credit (AMIC).

• Systems and automation - lead tax team's efforts on enterprise wide systems project such as SAP upgrades, and drive tax team standardization and adoption of tax technology tools including OTP, Alteryx, etc.

Additionally, the candidate will have a significant role in:
• Stakeholder management - Drive relationships with stakeholders including (a) internal business partners in the CFO office, Corp Planning, External Reporting, Treasury Accounting and other Tax Department groups, and (b) external parties such as statutory auditors.
• People leadership - Develop and lead the team, including mentoring, training and development of technical and finance skills, setting strategy and monitoring progress towards goals.Intel is looking for a candidate with the following:
• Knowledge of and experience with the preparation and review of US GAAP income tax provisions including ASC 740, accounting for uncertain tax positions, and accounting for the tax impacts of multiple M and A transactions.
• Experience with OneSource Tax Provision (OTP) or similar tax accounting software is a plus, as is a proven track record in process improvements, automation and ERP systems conversions.
• Experience managing corporate income tax compliance for multi-national and multi-state filings. Experience managing both insourced and outsourced compliance is ideal.
• Demonstrated success building, developing and leading a high performing team.
• Experience with partnership and R and D tax credits is a plus
• Experience with tax shared service centers or centers of excellence is also a plus.
• Proven ability to drive change in a large, fast paced and highly complex global organization.
• Strong analytical thinking and exceptional verbal and written communication skills.
• A collaborative and growth-oriented mindset.

Qualifications:

Minimum Qualifications

• Bachelor’s degree with 15+ years of relevant experience
• 12+ years of relevant experience focused on tax accounting and compliance from a combination of public accounting firm and in-house experience within a multinational company.

Preferred Qualifications

• Master’s degree in accounting or taxation and a CPA are both strongly preferred.

Experienced HireShift 1 (United States of America)US, California, Santa ClaraUS, Arizona, Phoenix, US, Oregon, Hillsboro
Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

You Are

Responsibilities may include but are not limited to:

• Performs functional verification of CPU logic to ensure design will meet specification requirements.

• Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to CPU microarchitecture specifications.

• Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs.

• Replicates, root causes, and debugs issues in the presilicon environment.

• Finds and implements corrective measures to resolve failing tests.

• Collaborates with CPU architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features and to meet functional, performance, and power goals.

• Documents test plans and drive technical reviews of plans and proofs with design and architecture teams.

• Maintains and improves existing functional verification infrastructure and methodology.

• Participates in the definition of architecture and microarchitecture features of the CPU being designed actively.

Qualifications:

You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Qualifications could be obtained through a combination of schoolwork, classes, research, and/or relevant previous job and/or internship experiences.

Minimum Qualifications

• The candidate must have a Bachelor's Degree in Electrical/Computer Engineering or any related field with 4+ years of relevant experience -OR- Master's in Electrical/Computer Engineering or any related field with 3+ years of relevant experience -OR- PhD in Electrical/Computer Engineering or any related field

• 3+ years of experience in Scripting languages such as Python and Perl,

• 3+ years of experience inComputer-Architecturefamiliarity

• 3+ years of experience in Power Management flows including low power entry/exit, frequency change flows etc

• 3+ years of experience in Design Verification and Validation methodologies with UVM, System Verilog and industry standard EDA tools

Preferred Qualifications

• Experience with Pre-silicon verification, SoC validation.

• Proficiency with C/C++ System Verilog coding and debug

• Experience with RTL development

• Knowledge of system level boot flows and power management.

Experienced HireShift 1 (United States of America)US, Arizona, PhoenixUS, Texas, Austin
Position of Trust

offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: