Fpga Silicon Dft Manager jobs at Intel in Malaysia

• Collaborate with technical, platform and business unit/product stakeholder groups to ensure supply chain is enabled and ready to deliver on time per test vehicle (TV) and/or product schedules.• Partner with internal technology segment Program Managers and others in the Substrate Business Group (SBG) to maintain the substrate sourcing strategy and manage TV and product line items within in.• Collect, vet, and distribute TV and new product introduction (NPI) quotes for new substrate designs. Maintain the quote database and SAP system setup with pricing.• Partner with TD team to balance (ROI) the cost/requirements imposed on suppliers by module requests. Highlight / escalate cost impacts.• Manage substrate engineering demand forecasts and distribute them to suppliers. Interpret supplier-report responses into actionable supply chain decisions to maximize Intel's ability to fulfill substrate demands.• Track substrate high volume manufacturing (HVM) readiness for products owned.• Facilitate supplier PO and invoice/payment resolutions when needed (working with Finance and Supplier Managers).• Manage and regularly report out SBG indicators regarding test vehicle or product substrate supply chain health.• Develops and executes commodity strategies, as well as drives supplier development through innovation and collaboration.• Maintains advanced knowledge of industry and market dynamics, and knowledge of commodities to drive supply chain solutions ahead of Intel's needs.• Owns relationships and coordinates purchasing activities with cross functional teams to acquire materials and services in a cost effective and timely manner.• Ensures that the respective commodity meets the business demand and cost requirements necessary for Intel to develop great products/services for its customers • Works with partner teams to capture commodity requirements and understand how design can influence cost and give feedback.• Leads sustainability and regulatory compliance and ensures suppliers comply with Intel's business processes
Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Bachelor's degree in Supply Chain Management, Business, technical or related field, or expect the required degree with 5+ years relevant experience
- or -
Master's degree in the same fields with 3+ years of relevant experienceRelevant work experience should be of the following:
• Project management skills or certification.
• Experienced in managing the overall strategy of the supplier account from initial selection, through product development, into high volume manufacturing HVM, and long-term sustaining support.
• Experienced in SAP enterprise or similar systems for order management and procurement.
• Skilled in planning and closing contract negotiations to achieve immediate and long-term affordability requirements.Preferred Qualifications:
• Experience with Semiconductor substrate manufacturing, supplier capability analysis and capacity expansion requirements
• Direct Supply Chain experience and, or technical degrees and experience are a plus.
• Lean Six Sigma is highly desired.

Experienced HireShift 1 (Malaysia)Malaysia, Penang

Job Description:

Manage and drive the Atom CPU post-si validation activities to align and meet goal and schedule of products.
The work encompasses:

• Define and manage validation plan and schedule with a thorough understanding of dependency management, key milestones, including critical path analysis.
• Aid in development, definition, and execution of POR that include schedules, budgets, resources, deliverables, and risks/mitigation.
• Provide assessment of Atom CPU health and manage key indicators.
• Represent Atom team to key project and validation forums.
• Facilitate meetings and reviews with stakeholders to drive validation readiness, execution, issue closures and risk mitigation.

Qualifications:

• Possess a BS/BE degree or higher with proven technical experience in engineering program management and understanding of silicon design.
• Possess have strong communication, collaboration and influencing skill.
• Certifications such as Project Management Professional (PMP) and experience in post-si validation will be an added advantage.

Experienced HireShift 1 (Malaysia)Malaysia, Penang

Qualifications:

You must possess a minimum of Bachelor Degree inElectrical/ElectronicsEngineering or Computer Engineering.

Additional qualifications include:

• Knowledge of Computer System Architecture.
• Knowledge in digital logic design, pre-silicon or post-silicon validation.
• Experience in tools and methodologies for pre-silicon verification/logic design including but not limited to: System Verilog, PERL/C/C++ programming, Synopsys simulator will be big plus.
• Strong analyzing and debugging skill, creative in problem solving.

Shift 1 (Malaysia)Malaysia, Penang

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

• Translates product requirements into package architecture specification, drives end-to-end package solutions for physical, electrical, and cost requirements.
• Leads technology tradeoff decisions ensuring silicon packages conform to electrical, mechanical, thermal, and reliability standards, specifications, and landing zones.
• Collaborates with silicon, hardware, and package leads to ensure high quality package output and aids in removing roadblocks.
• Oversees end-to-end package development process, including design, processes, and procedures and continuously improves packaging quality standards and targets.
• Applies expertise in package design troubleshooting, resolves new and existing packaging problems involving designs, materials, and processes and provides innovative and cost-effective solutions.
• Collaborates with manufacturing team to ensure the packaging design and tape-out seamlessly transition to production.

Qualifications:

• Bachelor Degree in relevant engineering/science domain with minimum 10 years of experience in the package design and/or architecture.
• Prior leadership role in package technology readiness development, design tape-out and/or innovation.

Experienced HireShift 1 (India)India, BangaloreMalaysia, Penang

Job Description:

• Translates product requirements into package architecture specification, drives end-to-end package solutions for physical, electrical, and cost requirements.
• Leads technology tradeoff decisions ensuring silicon packages conform to electrical, mechanical, thermal, and reliability standards, specifications, and landing zones.
• Collaborates with silicon, hardware, and package leads to ensure high quality package output and aids in removing roadblocks.
• Oversees end-to-end package development process, including design, processes, and procedures and continuously improves packaging quality standards and targets.
• Applies expertise in package design troubleshooting, resolves new and existing packaging problems involving designs, materials, and processes and provides innovative and cost-effective solutions.
• Collaborates with manufacturing team to ensure the packaging design and tape-out seamlessly transition to production.

Qualifications:

• Bachelor Degree in relevant engineering/science domain with minimum 10 years of experience in the package design and/or architecture.
• Prior leadership role in package technology readiness development, design tape-out and/or innovation.

Experienced HireShift 1 (Malaysia)Malaysia, Penang

Job Description:

• Develops the logic design, register transfer level (RTL) coding, simulation, and provides DFT timing closure support as well as test content generation and delivery to manufacturing for various DFx content (including BSCAN).
• Participates and collaborates in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed (including TAP, BSCAN, proc monitors, in system test/BIST).
• Develops HVM content for rapid bring up and ramp to production on the automatic test equipment (ATE). Applies various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT. Optimizes logic to qualify the design to meet power, performance, area, timing, test coverage, DPM, and test time/vector memory reduction goals as well as design integrity for physical implementation.
• Reviews the verification plan and drives verification of the DFT design to achieve desired architecture and microarchitecture specifications. Ensures design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
• Integrates DFT blocks into functional IP and SoC and supports SoC customers to ensure high quality integration of the IP block. Collaborates with post silicon and manufacturing team to verify the feature on silicon, support debug requirements, and document all learnings and improvements requirement in design and validation.
• Drives high test coverage through structural and specific IP tests to achieve the quality and DPM objectives of the product and develops HVM content for rapid bring up and production on the ATE.

Qualifications:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related fields.
• 5+ years of experience in DFT, SOC design, or related semiconductor design areas. Strong knowledge of DFT techniques, including BIST, boundary scan, JTAG, and fault simulation.
• Experience with EDA tools for DFT (e.g., Synopsys DFT Compiler, Mentor Tessent, Cadence Modus, ATPG).Proficiency in hardware description languages such as VHDL, Verilog, or System Verilog.
• Expertise in automated test generation and analysis tools. Strong problem-solving skills with the ability to troubleshoot complex testability issues. Experience with RTL design and verification processes.
• Excellent communication and teamwork skills to collaborate with multi-disciplinary teams. Ability to analyze, review, and optimize existing DFT strategies for design and test coverage. Familiarity with semiconductor manufacturing processes and test flows.

Preferred Qualifications :

• Experience with advanced test techniques such as DFT for low-power designs. Familiarity with industry standards such as IEEE 1687 (IJTAG), 1149.1 (JTAG), IEEE 1500 (Core Test), and others.
• Knowledge of Python or other scripting languages for automation.
• Experience with failure analysis, yield improvement and test cost optimization methodologies.
• Experience with SOC (System on Chip) or complex multi-chip designs requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and orschoolwork/classes/research.

Experienced HireShift 1 (Malaysia)Malaysia, Penang

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

• Builds emulation and FPGA models and solutions from RTL design using synthesis, partitioning, and routing tools.
• Develops, integrates, tests, and debugs hardware and software collateral in simulation, emulation, and FPGA models for testing new features, writes directed tests, develops the test environment and hybrid emulation environment, and supports verification of hardware and software/firmware.
• Defines and develops new capabilities and tools to achieve better verification through improved emulation and FPGA model usability.
• Enables acceleration of RTL development and improve emulation/FPGA model usability for presilicon verification, post silicon validation, and software development.
• Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform and interfaces with and provides guidance to verification teams for optimizing presilicon verification environments, test suites, and methodologies for emulation efficiency.
• Develops and utilizes automation aids, flows, and scripts in support of emulation utilization.
• Applies understanding of emulation and FPGA prototyping tools and methodologies, SoC integration, emulation transactors, emulation performance and optimization techniques, RTL simulation, and hybrid emulation environments (virtual platform and FPGA/emulation model).
• Collaborates with design, power and performance, silicon validation, and software teams, and participates in SoC and IP bring up, root causes testbench issues, IP and SoC testcases, and emulator/FPGA environment issues.

Qualifications:

• Bachelor’s or master’s degree in electronic and electrical engineering, Computer Engineering, or Mechatronics Engineering,
• Strong problem-solving and analytical skills.

Preferred Qualifications:

• Experience in RTL, FPGA, emulation, and SoC systems is a plus.
• Coursework or academic projects involving system-level validation, digital design, or emulation would be advantageous.
• Familiarity with FPGA tools (e.g., Xilinx Vivado, Intel Quartus) is a plus.
• Exposure to emulation platforms (e.g., Cadence Palladium, Synopsys ZeBu, Mentor Veloce) is desirable.

Shift 1 (Malaysia)Malaysia, Penang

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.