Ai Hw/sw Co-design Modelling Engineer jobs at Intel in Ireland

Key Responsibilities

• Execute all stages of the physical design flow, including:

• Synthesis

• Floorplanning

• Place and Route (P&R)

• Clock Tree Synthesis (CTS)

• Routing

• Static Timing Analysis (STA)

• Power and clock distribution

• Reliability and noise analysis

• Perform verification and signoff tasks such as:

• Formal equivalence verification

• Static and dynamic power integrity checks

• Layout verification

• Electrical Rule Checking (ERC)

• Analyze design results and recommend fixes for violations to support current and future product architectures.

• Optimize designs for power, performance, and area (PPA).

• Contribute to the development and automation of physical design methodologies and flows.

Required Skills & Experience

• Low power design techniques

• Physical/structural design flow

• Timing constraints

• Timing closure and physical clock design

• Proficiency with industry-standard EDA tools

• Bachelor’s (NFQ 8) or Master’s( NFQ 9)degree in Engineering or equivalent

In this position, you will become a member of the digital design team delivering next-generation NPUs for AI PCs. As part of this high-performance team, you will be involved in the digital design of super efficient, low power IP to run the latest AI models. The team is looking to hire an engineer with an interest in RTL development and in artificial intelligence.

Your responsibilities will include:

• Developing the micro-architectural specification of complex design block(s).
• Logic implementation of complex design block(s) using RTL coding techniques.
• Working with pre-Silicon validation engineers to develop cluster-level directed/random tests and environments.
• Working with the Physical Design (Layout) team on Synthesis, Formal Verification, and Timing Convergence.
• Interacting closely with other teams such as Architecture, DFx, Software, Firmware, and Post-Silicon Validation.

Required Experience:

• Exposure to RTL level Digital Design using System Verilog and/or Verilog.
• Proven track record of successful delivery of projects.
• A self-starter with the ability to manage your own time effectively and clearly communicate your ideas.
• Ability to work well in a diverse team environment.

• ExperienceinASIC, SoC, or FPGA design experience.
• Experience with industry-standard development tools and methodologies.
• Experience with languages such as C and/or C++, SystemC, OVM/UVM, SVAs, Perl, Shell scripting.
• Experience in some of the following areas/tools: Synthesis, Formal Verification, DFT, VCS, PrimeTime, Design Compiler, Jasper (FPV).
• Understanding topics such as model quantization, emerging data types etc., and their usage in inference for CNNs, LLMs and other deep learning models.

In this position, you will be a member of the silicon engineering division of the NEX Group. As part of this high-performance team, you will be involved in the digital design of leading-edge Cryptographic, Ethernet, and Packet Processing solutions on best-in-class Ethernet products. The team is looking to hire engineers with RTL development experience to augment and provide technical leadership within the existing team. Experience in adjacent engineering disciplines such as software development would also be considered.Responsibilities:

• Developing the micro-architectural specification of complex design block(s).

• Logic implementation of complex design block(s) using RTL coding techniques.

• Working with pre-Silicon validation engineers to develop cluster-level directed/random tests and environments.

• Working with the Physical Design (Layout) team on Synthesis, Formal Verification, and Timing Convergence.

• Interacting closely with other teams such as Architecture, DFx, Software, Firmware, and Post-Silicon Validation.

Educational Qualifications:

• At minimum, an Honours degree (level 8 on www.nfq.ie) in Electronic Engineering, Computer Science, or equivalent.

Required Experience:

• 6+ years of RTL level Digital IC Design experience using System Verilog and/or Verilog.

• Strong ASIC, SoC, or FPGA design experience.

• Proven track record of successful first-time delivery of projects.

• A self-starter with the ability to assume leadership roles.

• Ability to work well in a diverse team environment.

• Experience with industry-standard development tools and methodologies.

Preferred Experience:

• Experience with languages such as C and/or C++, SystemC, OVM/UVM, SVAs, Perl, Shell scripting.

• Experience in some of the following areas/tools: Synthesis, Formal Verification, DFT, VCS, PrimeTime, Design Compiler, Jasper (FPV).

Responsibilities:

• Conduct workload analysis and performance debugging to identify bottlenecks and drive resolution through hardware and/or software fixes.
• Evaluate AI-GPU hardware architecture and influence the product roadmap through a deep understanding of AI algorithms, customer needs, and software frameworks.
• Develop and enhance internal performance analysis tools.
• Develop highly optimized GPU kernels and software stacks, collaborating with partner teams to deliver high-performance solutions.
• Provide a comprehensive view of solutions and support both pre- and post-silicon activities.
• Collaborate with experts to analyse next-generation requirements and guide research and academic partnerships.

Minimum Qualifications:

• MS in Computer Engineering, Computer Science, Electrical Engineering, or Mathematics.
• 2-3 years of experience in GPU/CPU architecture for AI workloads.
• Proficient in Python, C/C++.Good data analysis and presentation skills.

Preferred Qualifications:

• Knowledge of AI and deep learning, including Large Language Models (LLM) and Stable Diffusion.
• Experience in performance analysis/performance debugging.
• Experience in building analytical and/or simulation-based performance models.
• Knowledge/experience in CPU, GPU, or memory design/architecture, and/ormicroarchitecture/RTL/design/processtechnologies.
• An aptitude to learn new things quickly in this fast-changing domain and flexibility to work on any mix of the above roles as needed.

This role is ideal for candidates who are eager to learn about AI hardware, possess strong collaboration skills, and can thrive in a fast-paced hardware/software development environment. Requirements listed would be obtained through a combination of industry-relevant job experience, internship experiences, and/orschoolwork/classes/research.

Join the FSO Yield Department as an Integration Engineer to work on these types of projects. FSO, the Far back end and Sort Organization, is a global organization that supports High-Volume Manufacturing (HVM) as well as Technology Development and Pathfinding activities related to Advanced Packaging.

FSO OR Integration Engineers areresponsiblefor the following duties:

• Ownership of the process heath and product quality of the FBE manufacturing line.

• Work with process modules to design, execute, and analyze experiments to sustain and improve the processes.

• Ownership of critical projects that span high volume manufacturing, process development, and fab-assembly package integration.

• Monitor and respond to end of line yield trends and execute baseline process changes.

• Defect Layer Owner Responsibilities - partner with Defect Metrology tool and system owners to identify and detect yield impactive defects, implement charts, limits, and lot/tool responses for OOCs.

• Must support Focus teams and Task forces by running experiments, analyzing data, and managing experiment logistics.

• Independently own projects and presentations to management.

• Collaborate with senior engineers in the group to play a key role executing process change implementations.

• Effectively work in a highly networked, cross organization role.

• Must be able to extract, analyze, summarize, and present data with recommendations.

• 24x7 on-call response (as part of an engineering rotation) to respond to urgent line issues, excursions, or to support task force-level projects.

The ideal candidate should exhibit the followingbehavioral traits:

• Learn new processes and flows.

• Make technical decisions and provide technical direction.

• Demonstrate strong listening, written, and verbal communication skills.

• Demonstrate effective communication up and down the organization, including skills to communicate technical issues and status to factory and program leadership.

• Evidence of organizational and planning skills for engineering projects.

• Team building skills.

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and orschoolwork/classes/research.

MinimumQualifications:

• Master's or Bachelor's degree in Physics, Chemistry, Materials Science, Electrical Engineering OR a comparable degree with 2+ years of experience in a semiconductor processing.

PreferredQualifications:

• Master of Science degree in Physics, Chemistry, Materials Science, Electrical Engineering, OR a comparable degree with 5+ years of experience in semiconductor processing or a technical leadership role.

• Integration, Defect Metrology, and / or Layer Owner Experience.

• Performs feasibility studies and provides integrated process solutions to meet desired safety, quality, reliability and output requirements for ultimate transfer to high volume manufacturing.

• Selects and develops material and equipment for the process to meet quality, reliability, cost, yield, productivity and manufacturability requirements.

• Plans and conducts experiments to fully characterize the process throughout the development cycle and to improve performance for each specific product.

• Identifies integrated process solutions to resolve issues or specific requests from customers by partnering with innovators in product engineering and module engineering teams.

• Conducts new product qualification and technology transfers from fabrication operations.

• Leverages big data analysis to identify process design weaknesses and/or manufacturing tool issues and proposes corrective, databased solutions.

• Collaborates and engages with development and material suppliers, and partners to develop processes and equipment needs to meet technology roadmaps.

You must possess the below minimum qualifications to be initially considered for this position.

Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:

• Bachelor's Degree in Electrical Engineering, Physics, Chemistry, Materials Science or in a STEM related Field.

• 9+ years of experience in advanced node semiconductor industry in BEOL Process Integration.

• 9+ years of experience with Device Physics and backend critical parameter control.

• 9+ years of experience with processes including lithography, dry etch, wet etch, CMP, diffusion, implant, thin films and metrology.

• Availability for at least 4 days on-site.

Preferred Qualifications:

• Experience in SADP/SAQP, advanced metallization, and/or immersion lithography/EUV).

• Advanced (Masters or PhD) degree in Electrical Engineering, Physics, Chemistry, Materials Science or in a STEM related Field.

• Experience in project/program management and/or Task Force Team lead.

• Experience in leveraging big data analysis to identify process design weaknesses and/or manufacturing weaknesses in order to propose corrective, data-based solutions.

• Experience with extracting insights from structured and unstructured data by quickly synthesizing large volumes of data and applying statistics and machine learning.

• Experience in new semiconductor technology development.

• Experience in serving external Foundry customers through technical interactions.

• Experience in latest lithography and metallization device architectures.

• Experience in Statistics and machine learning preferred.

• Previous related work experience in a semiconductor foundry preferred

FI/FA Engineersresponsibilitiesinclude (but are not limited to):

• Review incoming support requests and determine initial failure analysis / fault isolation workflow to identify and visualize root cause.

• Hands on operation of laboratory equipment, such as curve tracing, photon emission microscopy, laser stimulation (OBIRCH), and infrared imaging systems.

• Conduct failure analysis workflows using Ga and plasma FIBs, nanoprobing and sample preparation equipment. Mentor and coordinate workflows with supporting technicians.Interact with Transmission Electron Imaging (TEM) experts to interpret and explain failure root cause.

• Support continual improvement and development of new workstreams and techniques.

• Develop a thorough understanding of upstream and downstream techniques in the lab and work seamlessly with peers of different disciplines to get high quality results with fast throughput time.

• Present results of key analyses to internal and external customers.

Candidate should have the followingbehavioral skills:

• Demonstrated strength in teamwork, analytical problem solving, and effective oral and written communication skills.

• Inquisitive, desire to learn and expand knowledge in field.

• Ability to work with multi-functional, multi-cultural teams.

• Strong in decision making and problem solving.

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
MinimumQualifications:

• Bachelor's degree in science and engineering major with 4+ years' related lab experience

• Ireland candidates minimum Level 8 Bachelors' degree. or

• Masters degree in science and engineering major and 3+ years' related lab experience or

• Ph.D. in science and engineering major with 1+ years' related lab experience.

• and Experience working on silicon die or wafer level fault isolation / failure analysis.

PreferredQualifications

• Advanced degree (Master's or Ph.D.) in science and engineering major.

• 4+ years' experience in a semiconductor failure analysis laboratory supporting advanced technology node technology development.

• 4+ years' experience with 6T SRAM and logic failure analysis.

• Experience operating fault isolation and failure analysis tools.

• Understanding of FinFET technology architecture.

• Knowledge of wafer fabrication and general microelectronics.

• Knowledge of electrical and physical failure analysis flows for semiconductor.

• Hands on experience operating laboratory equipment.

• Willingness to work Front End or Back End Day Shifts

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and orschoolwork/classes/research.