Soc Design Verification Architect jobs at Intel in India, Bengaluru

Roles and Responsibilities include:

• Design and develop software features for AI frameworks—both hardware-agnostic and hardware-aware.
• Enhance and extend deep learning inference and training capabilities in the software stack.
• Analyze and architect state-of-the-art features across different frameworks and drive development across the full software stack.
• Identify optimization opportunities in the software stack to improve the performance of deep learning workloads.
• Participate in discussions with the open-source community, contribute to development, and upstream software enhancements.

Qualifications:

• B.Tech or M.S./M.Tech in CS, ECE, or related fields with 6–12 years of overall experience.
• Proficient in Python-based complex software implementations; intermediate knowledge of advanced C++ (C++14/17) and parallel programming.
• In-depth, hands-on experience with frameworks such as PyTorch, vLLM, and SGLang.
• Experience with advanced inference-serving features such as disaggregated serving, quantization, speculative decoding, and constrained decoding.
• Strong understanding of LLMs
• Practical knowledge of deep learning models for image and video generation is desirable.
• Ability to debug complex issues in multi-layered software systems; understanding of software integration in large open-source frameworks.
• Strong understanding of computer architecture and HW-SW optimization techniques.
• Effective communication skills and experience working in cross-geo teams.
• Ability to perform performance analysis of code on both host and accelerators/GPUs using open-source and proprietary profilers.
• Understanding of the competitive landscape for technologies in this domain.

Preferred

• Experience developing and integrating CUTLASS or Triton-based kernels for deep learning.
• Knowledge of compiler algorithms for heterogeneous systems and fuser optimizations.

Experienced HireShift 1 (India)India, Bangalore

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

• Performs functional logic verification of an integrated SoC to ensure design will meet specifications.
• Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications.
• Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment.
• Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features.
• Documents test plans and drives technical reviews of plans and proofs with design and architecture teams.
• Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage.
• Maintains and improves existing functional verification infrastructure and methodology.
• Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products.

Qualifications:

• Must have either a BS + 15 years' experience or MS + 13 years' experience in Computer Science, Computer Engineering or Electrical Engineering.Minimum 10 years' experience working on Validation, verification, or integration using Verilog/System Verilog.
• Minimum 13 years' experience with writing validation plans and software to implement those validation plans.
• Minimum 8 years' experience with an object-oriented programming language. Minimum 8 years' experience with Verilog or other HDL.
• Minimum 5 years' experience with UNIX or Linux.

Required Skill -

• Minimum 14 years with validation experience.
• Exposure toGraphics/Media/Display/SOCSecurity features is highly desired with strong expertise in any of these domains.

Experienced HireShift 1 (India)India, Bangalore

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

• Performs physical design implementation of CPU designs from RTL to GDS to create a design database that is ready for manufacturing.
• Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
• Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
• Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams.
• Possesses CPU specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT.
• Works intimately with industry EDA vendors to build and enhance tool capabilities to design a highspeed, low power synthesizable CPU.
• Optimizes CPU design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.

Qualifications:

• B.Tech. or M.Tech. inElectrical/ElectronicsEngineering with 8-12+ years' of experience.
• Key skills: Experience in all aspects of physical design flow in SOC using Synopsys and cadence tools.
• Experience in timing signoff, formal verification and low power static signoff.
• Experience in all aspects of clock distribution.
• Experience in deep submicron process technology nodes is strongly preferred.
• Solid understanding of power delivery and power plane distributions, power estimation and optimization in SOC.
• Solid understanding industry standard tools for synthesis, place and route and tape out flows.Solid understanding of physical design verification methods to debug LVS/DRC.

Experienced HireShift 1 (India)India, Bangalore

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Key Responsibilities

• DevelopSystemVerilog/UVM-basedtestbenches for IP, subsystem, or SoC-level verification.
• Create and maintain verification plans, test cases, and coverage models.
• Implement and integrate scoreboards, monitors, checkers, assertions, and transactors for functional correctness.
• Work with Verification IP (VIP) for industry-standard protocols (AMBA, UCIe, PCIe, DDR, Ethernet, etc.) and integrate them into testbenches.
• Build reusable constrained-random and directed test scenarios.
• Debug failures, perform root cause analysis, and work closely with design and architecture teams.
• Analyze functional coverage, code coverage, and assertion coverage to ensure verification completeness.
• Participate in design/verification reviews and contribute to methodology improvements.
• Automate regression runs and maintain CI verification flows (Jenkins, Git, etc. if applicable).

Required Skills & Qualifications:

• Bachelor’s/Master’s inElectrical/Electronics/ComputerEngineering or related field with 8+ years of experience.
• Strong hands-on experience with SystemVerilog and UVM methodology.
• Proven experience in transactor modeling and VIPintegration/customization.
• Good understanding of digital design fundamentals (RTL, FSMs, buses, etc.).
• Familiarity with coverage-drivenverification andconstraint random test generation.
• Proficiency with industry-standard simulators and/or emulators (Synopsys VCS/Zebu, Cadence Xcelium/Palladium, Mentor Questa/Veloce, etc.).
• Debugging skills using waveforms and verification tools.
• Exposure to SVA (SystemVerilog Assertions) and functional coverage techniques.
• Experience withC/C++/Python fortestbench integration or automation.
• Hands-on work with protocol VIPs (AXI, AHB, APB, UCIe, PCIe, DDR, Ethernet, USB, etc.).
• Strong communication and teamwork skills.
• Experience in applying AI tools forverification/validationis a plus

Experienced HireShift 1 (India)India, Bangalore

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

• Directs and manages a team of formal verification engineers responsible for IP and SoC design verification.
• Deploys and manages leading formal verification processes, procedures, verification tools, and technologies based on latest model and algorithms.
• Possesses subject matter expertise in formal verification principles, methods, and relevant standard industry practices.
• Oversees definition, boundaries and performance of formal verification, proper test planning, tracking, and evaluating ROI.
• Works with design and microarchitecture teams to identify design bugs and improve overall microarchitecture.
• Manages stakeholders, works with respective IP/SoC teams, keeps them updated on the progress, and drives problem scoping and solution.
• Responsible for enabling teams to execute through clear goal setting, facilitating work, maintaining accountability, applying differentiated performance management, and driving team results.
• Drives results by inspiring people, role modeling Intel values, developing the capabilities of others, and ensuring a productive work environment.

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications:

• Year of experience: 8+ with minimum of 4 years in formal execution.

Preferred Qualifications:

• Project management experience is plus
• Leading team in formal verification execution is must.
• Having hands experience in execution and the candidate will be contributing to some of the execution.

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and orschoolwork/classes/research.

Experienced HireShift 1 (India)India, Bangalore

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

• As an IP Structural/Physical Design Engineer, you will be working alongside Elite IP and SoC design teams to deliver next-generation Xeon products and related IPs for Server markets. We are looking for candidates with experience as physical design engineers as part of the Structural Design Expert Team in the IP organization.
• You will be fluent in all aspects of IP physical design flow from high-level block design to synthesis, place and route and timing and power convergence to build a design database that is ready for manufacturing. Your responsibilities will include all aspects of RTL2GDSII physical design flow convergence including but not be limited to: Oversees definition, design, verification, and documentation for SoC (System on a Chip) development.
• Block-level floor planning, interconnect planning and UPF based power delivery methodology. Logic synthesis of design blocks using Synopsys Design Compiler DCT- Formal Equivalence Verification FEV using Cadence's Conformal tool.
• Auto Place-and-Route APR using Synopsys Fusion Compiler tools. Timing and power verification using Synopsys PrimeTime as well as Intel tools. Layout Verification and DRC analysis. What we offer: We give you opportunities to transform technology and create a better future, by delivering products that touch the lives of every person on earth.
• As a global leader in innovation and new technology, we foster a collaborative, supportive, and exciting environment where the brightest minds in the world come together to achieve exceptional results. We offer a competitive salary and financial benefits such as bonuses, life and disability insurance, opportunities to buy Intel stock at a discounted rate, and Intel stock awards (eligibility at the discretion of Intel Corporation).
• We provide benefits that promote a healthy, enjoyable life: excellent medical plans, wellness programs, and amenities, time off, recreational activities, discounts on various products and services, and much more creative perks that make Intel a Great Place to Work. We're constantly working on making a more connected and intelligent future, and we need your help.Change tomorrow. Start today.

Qualifications:

• Candidate must have a Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science,with atleast 7+ yearsof experience listed below. OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, with 6+ years of experience listed below.
• Related field experience in CMOS circuit design, and layout verification. Industry standard CAD tools/flows for digital design.

Preferred Qualifications:

• Experience in Fusion Compiler / Primetime Process and Design co-optimization for Density/Performance improvements, RTL based power estimation and optimization.
• Experience in CPU/ASIC design methodology and flow development, particularly in the RLS, Structural Design, APR and low power optimization domains.
• Unix skills, programming skills in Python, Perl Script and shell scripting.
• Good understanding of overall CPU/SOC design cycle and requirements.
• Experience in working on high frequency designs and methodologies.
• Candidate should be willing to multi-task and flexibility to work in a global environment.
• Good communication skills and have self-motivation.
• Good analytical and Problem solving skills.
• Experience in working on high frequency designs and methodologies.
• Experience in leading small teams to design IPs.

Experienced HireShift 1 (India)India, Bangalore

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products.Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications:Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 8+ years of technical experience.Related technical experience should be in/with: Silicon Design and/orPreferred Qualifications:Design and/or Design Verification with developing, maintaining, and executing complex IPs and/or SOCs.Experience in PreSilicon Performance Verification OVM/UVM, System Verilog, constrained random verification methodologies.The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure).Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies.Experience in Xeon CPU Pre-Silicon or Post Silicon Validation.Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and orExperienced HireShift 1 (India)India, Bangalore

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.