Reliability Verification Lead jobs at Intel in India, Bengaluru

Job Description:

• Performs functional logic verification of an integrated SoC to ensure design will meet specifications.
• Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications.
• Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment.
• Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features.
• Documents test plans and drives technical reviews of plans and proofs with design and architecture teams.
• Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage.
• Maintains and improves existing functional verification infrastructure and methodology.
• Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products.

Qualifications:

• Must have either a BS + 15 years' experience or MS + 13 years' experience in Computer Science, Computer Engineering or Electrical Engineering.Minimum 10 years' experience working on Validation, verification, or integration using Verilog/System Verilog.
• Minimum 13 years' experience with writing validation plans and software to implement those validation plans.
• Minimum 8 years' experience with an object-oriented programming language. Minimum 8 years' experience with Verilog or other HDL.
• Minimum 5 years' experience with UNIX or Linux.

Required Skill -

• Minimum 14 years with validation experience.
• Exposure toGraphics/Media/Display/SOCSecurity features is highly desired with strong expertise in any of these domains.

Experienced HireShift 1 (India)India, Bangalore

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

• Performs physical design implementation of CPU designs from RTL to GDS to create a design database that is ready for manufacturing.
• Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
• Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
• Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams.
• Possesses CPU specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT.
• Works intimately with industry EDA vendors to build and enhance tool capabilities to design a highspeed, low power synthesizable CPU.
• Optimizes CPU design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.

Qualifications:

• B.Tech. or M.Tech. inElectrical/ElectronicsEngineering with 8-12+ years' of experience.
• Key skills: Experience in all aspects of physical design flow in SOC using Synopsys and cadence tools.
• Experience in timing signoff, formal verification and low power static signoff.
• Experience in all aspects of clock distribution.
• Experience in deep submicron process technology nodes is strongly preferred.
• Solid understanding of power delivery and power plane distributions, power estimation and optimization in SOC.
• Solid understanding industry standard tools for synthesis, place and route and tape out flows.Solid understanding of physical design verification methods to debug LVS/DRC.

Experienced HireShift 1 (India)India, Bangalore

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Key Responsibilities

• DevelopSystemVerilog/UVM-basedtestbenches for IP, subsystem, or SoC-level verification.
• Create and maintain verification plans, test cases, and coverage models.
• Implement and integrate scoreboards, monitors, checkers, assertions, and transactors for functional correctness.
• Work with Verification IP (VIP) for industry-standard protocols (AMBA, UCIe, PCIe, DDR, Ethernet, etc.) and integrate them into testbenches.
• Build reusable constrained-random and directed test scenarios.
• Debug failures, perform root cause analysis, and work closely with design and architecture teams.
• Analyze functional coverage, code coverage, and assertion coverage to ensure verification completeness.
• Participate in design/verification reviews and contribute to methodology improvements.
• Automate regression runs and maintain CI verification flows (Jenkins, Git, etc. if applicable).

Required Skills & Qualifications:

• Bachelor’s/Master’s inElectrical/Electronics/ComputerEngineering or related field with 8+ years of experience.
• Strong hands-on experience with SystemVerilog and UVM methodology.
• Proven experience in transactor modeling and VIPintegration/customization.
• Good understanding of digital design fundamentals (RTL, FSMs, buses, etc.).
• Familiarity with coverage-drivenverification andconstraint random test generation.
• Proficiency with industry-standard simulators and/or emulators (Synopsys VCS/Zebu, Cadence Xcelium/Palladium, Mentor Questa/Veloce, etc.).
• Debugging skills using waveforms and verification tools.
• Exposure to SVA (SystemVerilog Assertions) and functional coverage techniques.
• Experience withC/C++/Python fortestbench integration or automation.
• Hands-on work with protocol VIPs (AXI, AHB, APB, UCIe, PCIe, DDR, Ethernet, USB, etc.).
• Strong communication and teamwork skills.
• Experience in applying AI tools forverification/validationis a plus

Experienced HireShift 1 (India)India, Bangalore

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

• Directs and manages a team of formal verification engineers responsible for IP and SoC design verification.
• Deploys and manages leading formal verification processes, procedures, verification tools, and technologies based on latest model and algorithms.
• Possesses subject matter expertise in formal verification principles, methods, and relevant standard industry practices.
• Oversees definition, boundaries and performance of formal verification, proper test planning, tracking, and evaluating ROI.
• Works with design and microarchitecture teams to identify design bugs and improve overall microarchitecture.
• Manages stakeholders, works with respective IP/SoC teams, keeps them updated on the progress, and drives problem scoping and solution.
• Responsible for enabling teams to execute through clear goal setting, facilitating work, maintaining accountability, applying differentiated performance management, and driving team results.
• Drives results by inspiring people, role modeling Intel values, developing the capabilities of others, and ensuring a productive work environment.

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications:

• Year of experience: 8+ with minimum of 4 years in formal execution.

Preferred Qualifications:

• Project management experience is plus
• Leading team in formal verification execution is must.
• Having hands experience in execution and the candidate will be contributing to some of the execution.

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and orschoolwork/classes/research.

Experienced HireShift 1 (India)India, Bangalore

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

• You will be part of ACE India , in the P- Core design team driving Intel's latest CPU's in the latest process technology.
• As a DFT engineer direct responsibilities of the role, but not limited to, working on various aspects of PCORE DFT including Spyglass DFT, RTL implementation, Verification, Scan, and ATPG.
• The candidate must be able to drive the DFT implementation for various features incl Scan, MBIST, TAP, etc.
• Previous experience working with manufacturing engineering, pattern delivery, and post-silicon support is a definite plus.

Qualifications:

• Candidate must possess a Master's degree in Electronics or Computer Engineering with at least 7 or more years of experience or a bachelor's degree with at least 9 years of experience in DFT.
• Strong knowledge of ATPG, various fault models, fault grading.
• Knowledge of memory BIST, IJTAG/TAP architecture.
• DFT logic generation, integration, and verification.
• EDA vendor-supported scan architectures and tools, covering synthesis, timing, DRC, ATPG, GLS (Unit delay and Timing/SDF based), and tester bring uppreferably.
• Mentor/Siemens Tessent Shell, TestKompress, ATPG coverage debug.
• Experience in Design Verification (DV) using standard simulators e.g. VCS, Verdi waveform viewer.
• Post Silicon/ATE Bring-Up Support.
• Experience with RTL (Verilog, System Verilog, VHDL)

Experienced HireShift 1 (India)India, Bangalore

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products.Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications:Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 8+ years of technical experience.Related technical experience should be in/with: Silicon Design and/orPreferred Qualifications:Design and/or Design Verification with developing, maintaining, and executing complex IPs and/or SOCs.Experience in PreSilicon Performance Verification OVM/UVM, System Verilog, constrained random verification methodologies.The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure).Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies.Experience in Xeon CPU Pre-Silicon or Post Silicon Validation.Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and orExperienced HireShift 1 (India)India, Bangalore

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

Come join Intel's Design Development Group organization as an SOC Verification engineering focused on Design for Debug (DFD). As a member of the product team, you will work firsthand with multi-function teams/sites, implementing and validating state-of-the-art debug solutions appropriate for new and existing technology in the product. In this role you will be working as part of a pre-silicon validation team for future Intel SoCs or IPs, focusing on debug validation. You will be working with pre-silicon and post -silicon validation teams to improve debug features and tools suites. You will also work closely with post-silicon validation SW teams on debug tool validation and silicon enabling. You will be pioneering new debug tools and flows, reviewing and publishing architectural specs and supporting next-generation silicon enabling on system platforms.Your responsibilities will include but not be limited to:

• Verification of Design for Debug features (e.g. low and high-bandwidth signal tracing and event triggering) using simulation, emulation, and/or FPGA.
• Creating test plans and tests for validating portions of a complex microarchitecture using written specs, RTL code and other tests as a guide.
• Learning Power Management, Memory and debug architecture and microarchitecture by debugging failures to the root cause.
• Developing and utilizing various debug and validation tools and/or methodologies to implement validation plans with the goal being to ensure a solid design.
• Participating in the debug of failures on silicon and developing new testing strategies to detect these failures on RTL models.
• Developing debugging tools and software.

Minimum Qualifications:

• Candidate must have either a BE /ME / MTech or MS in Electronics, VLSI, Microelectronics, Computer Science or Electrical Engineering with 4-10 Years of experience.
• Extensive Pre-silicon Track record of driving debug tools enabling and validation, improvements and getting them adopted by others.
• Proven record of working across verification teams to solve problems.
• Expert of HW and SW Interaction and debug to root cause.
• Experience working across verification, architecture, SW, and design teams to resolve debug issues.
  Minimum 4 years of experience with writing verification plans and testcases to implement those validation plans.
• Minimum 4years of SOC Verification or Functional verification.
• Minimum 2yrs experience with Programming languages/Scripting: C, Perl, Python, Verilog and UNIX or Linux.
• Minimum 2yrs experience with SOC Architecture.
• Must have 4yrs+ experience with SOC Verification or Functional Verification.
• Must have 4yrs+ experience with validation or testing experience, especially in a silicon design team.

Preferred Qualifications

• Good to have 2yrs+ experience with industry standards such as JTAG, Tessent and Debug architecture.
• Good to have working experience on assertions, coverage and Formal verification

Experienced HireShift 1 (India)India, Bangalore

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.