Asic Flow Methodology Lead jobs at Intel in India, Bengaluru

Job Description:

• Performs physical design implementation of CPU designs from RTL to GDS to create a design database that is ready for manufacturing.
• Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
• Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
• Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams.
• Possesses CPU specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT.
• Works intimately with industry EDA vendors to build and enhance tool capabilities to design a highspeed, low power synthesizable CPU.
• Optimizes CPU design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.

Qualifications:

• B.Tech. or M.Tech. inElectrical/ElectronicsEngineering with 8-12+ years' of experience.
• Key skills: Experience in all aspects of physical design flow in SOC using Synopsys and cadence tools.
• Experience in timing signoff, formal verification and low power static signoff.
• Experience in all aspects of clock distribution.
• Experience in deep submicron process technology nodes is strongly preferred.
• Solid understanding of power delivery and power plane distributions, power estimation and optimization in SOC.
• Solid understanding industry standard tools for synthesis, place and route and tape out flows.Solid understanding of physical design verification methods to debug LVS/DRC.

Experienced HireShift 1 (India)India, Bangalore

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

• You will be part of ACE India , in the P- Core design team driving Intel's latest CPU's in the latest process technology.
• As a DFT engineer direct responsibilities of the role, but not limited to, working on various aspects of PCORE DFT including Spyglass DFT, RTL implementation, Verification, Scan, and ATPG.
• The candidate must be able to drive the DFT implementation for various features incl Scan, MBIST, TAP, etc.
• Previous experience working with manufacturing engineering, pattern delivery, and post-silicon support is a definite plus.

Qualifications:

• Candidate must possess a Master's degree in Electronics or Computer Engineering with at least 7 or more years of experience or a bachelor's degree with at least 9 years of experience in DFT.
• Strong knowledge of ATPG, various fault models, fault grading.
• Knowledge of memory BIST, IJTAG/TAP architecture.
• DFT logic generation, integration, and verification.
• EDA vendor-supported scan architectures and tools, covering synthesis, timing, DRC, ATPG, GLS (Unit delay and Timing/SDF based), and tester bring uppreferably.
• Mentor/Siemens Tessent Shell, TestKompress, ATPG coverage debug.
• Experience in Design Verification (DV) using standard simulators e.g. VCS, Verdi waveform viewer.
• Post Silicon/ATE Bring-Up Support.
• Experience with RTL (Verilog, System Verilog, VHDL)

Experienced HireShift 1 (India)India, Bangalore

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

• The Client Development Group Bangalore, India is looking for a highly motivated SOC Pre-Si Verification Lead to join the compute die frontend DV team for the next generation of Client SOC.
• ResponsibilitiesOwn or lead verification of complex flows at the SOC, subsystem, or IP levelsLearn about the design and interact with partner teams to define verification strategies and test plans.
• Develop verification environments and run and debug simulations to drive quality.
• Apply random-stimulus and coverage-based techniques to find bugs and meet test plan goals.
• Innovate to improve verification efficiency through methodologies or tools Coach and mentor team in your areas of expertise.
• Demonstrate core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity and Inclusion.
• Plan the verification of complex design IP/SS/SoC interacting with the architecture and design engineers to identify verification test scenarios.
• Facilitate interactions with cross functional engineering organizations in supporting Project execution.
• Project planning and scheduling of activities of local team and present and report progress on a regular basis.
• Develop strategies, provide guidance and support team in addressing failure events.Formal : Good to have hands-on experience with formal verification .

Qualifications:

• 7+ years of experience in design verification with a proven track record of delivering complex CPU or SoC IP's/SS.
• Experience with verification for multiple product cycles from definition to silicon, including writing test plans, developing tests, debugging failures and coverage signoff in SV-UVM.
• Substantial background in debugging RTL (Verilog) designs as well as simulation and/or emulation environments
• Desirable
• Knowledge in SoC high-speed IO protocols, Fabric-NOC, MemSS, Graphics, Multimedia, Coherency cluster integration and System level flows verification.
• Hands-on experience with formal verification.
• Experience of working on x86 arch based High performing/Low Power SoCs.
• Scripting language such as Python or Perl.

Experienced HireShift 1 (India)India, Bangalore

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products.BE/Btech/MTech with 12plus years of experience
Experienced HireShift 1 (India)India, BangaloreXeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.

Job Description:

We're looking for a highly motivated, Pre-Silicon Verification Engineer who is responsible to ensure:

• Development of Complex Pre-Silicon Verification environment
• Development of Verification Components and coverage plans
• Write and execute validation Plans to ensure Right First Time Success of our Products
• Work directly with hardware architects, logic designers to influence overall SoC and system design.

Qualifications:

Candidate must possess a master's degree in Electronics or Computer Engineering with at least 8+ or more years of experience in related field.Preferred Qualifications:

• Experience in Processor verification
• Experience with Specman/SV Language is plus
• Experience in verifying Power Mgmt, Cache controllers and memory features is plus
• Experience with Formal verification techniques is a plus
• Strong background in scripting - PERL/Python
• System hardware and software debug skills
• Understanding of software and/or hardware validation techniques
• Solid understanding of system and processor architecture, and the interaction of computer hardware with software.

Experienced HireShift 1 (India)India, Bangalore

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

• You will be part of ACE India , in the P- Core design team driving Intel's latest CPU's in the latest process technology.
• In this position, you will be responsible for leading the design analysis and methodologies of the different types of memory blocks.
• Your responsibilities will include but not limited to and nbsp
• Responsible for methodology enablement for memory blocks to meet over 5GHz Freq and low-power digital designs with optimal area.
• In depth understanding of different memory design concepts ((SRAM/RF/ROM).
• Expertise in Static timing analysis concepts.
• Close work with Layout and Floor planning teams.
• Back end design implementation of new features and nbsp.
• Expertise in Memory post silicon analysis.
• Good understanding of statistical variation.
• Planning, implementing and analyzing clock distribution from Full Chip level to leaf level for CPU cores.

Qualifications:

• You must possess a master's degree in electrical or computer engineering with atleast 8 or more years of experience in related field or a bachelor's degree with atleast 10 years of experience.
• Technical Expertise in synthesis, P and R tools preferred.

Preferred Qualifications:

• Digital Design Experience, with High Speed, Low Power.
• Familiarity with Verilog/VHDL.
• Tcl, Perl, Python scripting.
• Good understanding of spice simulations and analysis
• Custom circuit design, IO design, full chip clocking6. Strong verbal and written communication skills.
• Experience in design & verification of high-speed clocks.
• This role requires hands-on knowledge with hierarchical designs, budgeting of latencies and skews.

Experienced HireShift 1 (India)India, Bangalore

Job Description:

• Development, enablement, and deployment of static EOS (electrical overstress) rule decks for Intel Foundry.
• Basic knowledge of PDK and rule deck development is a must.
• Enablement, Validation and Foundry Certifications of Industry Standard EDA Reliability (EM/IR) tools.
• Collaborate with multiple stakeholders to ensure EOS rules are accurately integrated into the design and deployed with PDK. Perform updates and optimizations to the rule deck to accommodate new technology features.
• Troubleshoot and resolve issues related to EOS ruledeck and EM/IR implementation and execution.
• Communicate effectively with stakeholders to provide updates on progress, challenges, and solutions related to EOS HV and EM/IR checks.
• Ensure reliability by performing high-voltage static checks on schematic designs at both the device and template levels, before it gets deployed to customer.
  Stay updated with industry trends and advancements in VLSI industry precisely in Reliability domain.
• Write good documents for EOS/HV and EM/IR flows and PDK. Train the users and design engineers on EOS/HV and EM/IR flows.
• Self-motivated, strong leadership skills being able to influence across internal and external ecosystem
• Able to work with cross-functional and cross site teams and influence multiple internal and external stakeholders.

Qualifications:

• BTech/BE in EE/CE with 7+ relevant industry experience OR MTech/ME in EE/CE with 5+ relevant industry experience in the following areas:
• Basic Reliability concepts like Electro Migration (EM), IR Drop, Temperature Effects.
  PVT - EM/IR Inter links, Digital Design Sign off expertise/basic knowledge is essential.
• Exposure to minimum of one Digital RV tools in any one major Industry standard EDA Tool (Cadence Voltus/Ansys RHSC) and its working.
• CMOS device physics, process technology and design rules
• Good experience in rule deck development and scripting languages: Python, PERL, TCL
• Good experience in PERC, ERC, SVRF, HV EOS and EM/IR flow methodologies.

Experienced HireShift 1 (India)India, Bangalore