Physical Design Engineer Static Timing Analysis jobs at Google in Israel, Tel Aviv-yafo
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Israel
Tel Aviv-yafo
410 jobs found
25.09.2024
G
Google Physical Design Engineer Static Timing Analysis Israel, Tel Aviv District, Tel Aviv-Yafo
Bachelor's degree in Electrical Engineering or equivalent practical experience. Experience in RTL2GDS, Static Timing Analysis (STA) flows, and methodologies. Experience with physical design tools (e.g., Synopsys, Cadence) and timing signoff...
Bachelor's degree in Electrical Engineering, Chemical Engineering, Physics, Chemistry, Material Science, a related field, or equivalent practical experience. 4 years of experience in ASIC physical design flows and methodologies in...
Bachelor's degree in Electrical Engineering, Chemical Engineering, Physics, Chemistry, Material Science, a related field, or equivalent practical experience. 4 years of experience in ASIC physical design flows and methodologies in...
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 3 years of experience with digital logic design principles, RTL design concepts, and languages...
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 3 years of experience with digital logic design principles, RTL design concepts, and languages...
Bachelor's degree in Electrical Engineering or equivalent practical experience. Experience verifying digital logic at RTL level using SystemVerilog, or Specman/E for FPGAs or ASICs. Experience verifying digital systems using standard...
Bachelor’s degree in Electrical Engineering or equivalent practical experience. 4 years of experience in power delivery network design and verification in nodes technologies. Experience with Electromigration (EM)/IR tools (e.g., RedHawk-SC,...
Bachelor's degree in Electrical Engineering or equivalent practical experience. Experience in RTL2GDS, Static Timing Analysis (STA) flows, and methodologies. Experience with physical design tools (e.g., Synopsys, Cadence) and timing signoff...
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