Senior Analog/mixed jobs at Cisco in United States, San Jose
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Company (1)
Job type
Job categories
Job title (1)
United States
State
San Jose
64 jobs found
17.12.2024
C
Cisco Senior ASIC Design Engineer United States, California, San Jose
Write micro-architecture specifications and participate in reviews. Implement Verilog RTL to meet timing, performance, and power requirements. Contribute to full chip integration and timing methodology/analysis. Develop and analyze functional coverage....
Create and design scalable, secure solutions that meethigh standardsof quality and efficiency. Collaborate closely with designers and product managers to deliver impactful production experiences. Plan, design, and execute high-quality feature...
Lead deployment efforts for select accounts, collaborating with partners (application and device providers), customers, sales teams, and system integrators. Develop and maintain runbooks, technical documentation, and enablement materials to standardize...
Join forces with the software engineers to ensure that the ThousandEyes platform’s Federal region infrastructure and services are designed and optimized for availability, latency, and performance. Design, implementation, and management...
Experience with memory architectures and access optimization will be useful. Strong interpersonal skills, both written and verbal, networking protocol knowledge. Excellent analytical and decision-making skills. Independent, proactive with an ability...
Bachelor’s degree with 8+ or a Master’s degrees with 6+ years of experience in computer science engineering or equivalent. Analyze and improve the performance of existing systems by applying data...
Develop architecture, author PRDs, and participate in RFQs for our wireless access point portfolio. Validate and iterate on layout and schematics. Drive vendors on component selection, qualification, and FA. Control...
Write micro-architecture specifications and participate in reviews. Implement Verilog RTL to meet timing, performance, and power requirements. Contribute to full chip integration and timing methodology/analysis. Develop and analyze functional coverage....
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