Director Technical Program Management jobs at Cisco in United States, San Jose
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Company (1)
Job type
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Job title (1)
United States
State
San Jose
107 jobs found
29.01.2025
C
Cisco ASIC Design Engineer Senior Technical Leader United States, California, San Jose
Participate in and contribute to chip architecture definition and discussions. Author design specifications and participate in micro-architecture specification reviews. Implement Verilog RTL to meet timing and performance requirements. Help define,...
Lead CHG product team and drive a competitive product roadmap. Partner with architecture and execution teams, system architects, Cisco networking product and engineering teams, and external ASIC customers. Through those...
Design and develop thermal solutions (air-cooled or liquid-cooled) for systems with high-power ASICs and high-density optical transceivers. Develop detailed package, board, and system-level simulations using Computational Fluid Dynamic tools such...
Bachelor’s degree in computer science, Computer Engineering, Electrical Engineering, or related degree and 8+ years of experience in an Engineering role or Master's degree or related with 6+ years of...
Optimize and maintain builds and CI/CD pipelines using your expertise in Jenkins, Gradle, Docker, and Kubernetes. Develop tooling to collect diagnostic data from test pipelines. Extract health metrics from the...
Previous experience working with or for Webscale companies in roles or functions related to product management, engineering, test or validation. Deep and broad knowledge of current and emerging technologies that...
Leading discussions with customers and gathering technical requirements. Building out testing environments for system/solution validation. Developing and enhancing test frameworks and benchmarking tools. Defining and gathering data for network performance...
Participate in and contribute to chip architecture definition and discussions. Author design specifications and participate in micro-architecture specification reviews. Implement Verilog RTL to meet timing and performance requirements. Help define,...
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