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Asic Design Verification jobs at Cisco in United States, San Jose
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United States
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San Jose
48 jobs found
17.12.2024
C
Cisco ASIC Engineering Technical Leader United States, California, San Jose
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Architect block, cluster and top level DV environment infrastructure. Create DV infrastructure from scratch for block, cluster and top level environments. Maintaining existing DV environments and enhancing them. Ensuring complete...
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17.12.2024
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Cisco Senior ASIC Design Engineer United States, California, San Jose
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Write micro-architecture specifications and participate in reviews. Implement Verilog RTL to meet timing, performance, and power requirements. Contribute to full chip integration and timing methodology/analysis. Develop and analyze functional coverage....
17.12.2024
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Cisco ASIC Design Technical Leader – & Timing Constraints Focus United States, California, San Jose
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Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes. Option to also do...
17.12.2024
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Cisco ASIC Design Test United States, California, San Diego
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Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs. Responsible for development of innovative DFT IP in collaboration with...
17.12.2024
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Cisco ASIC Design Test Engineer United States, California, San Jose
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Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs. Responsible for development of innovative DFT IP in collaboration with...
16.12.2024
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Cisco ASIC STA Engineering Technical Leader United States, California, San Jose
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Leading architecture design and optimization in the early stages of chip development, focusing on timing context and budgeting for enhanced performance. Developing and refining timing and sign-off methodologies, driving the...
16.12.2024
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Cisco ASIC Verification Engineer United States, California, San Jose
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BSEE/CS combined with 4+ years of related experience. 4+ Years post graduate hands on experience with System Verilog / UVM programming. 4+ Years post graduate ASIC Verification processes, methodologies, flows...
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Description:Full job details
Architect block, cluster and top level DV environment infrastructure. Create DV infrastructure from scratch for block, cluster and top level environments. Maintaining existing DV environments and enhancing them. Ensuring complete...
These jobs might be a good fit
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