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Asic Design Test jobs at Cisco in United States, San Jose
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San Jose
23 jobs found
15.09.2024
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Cisco ASIC Design Test United States, California, San Jose
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Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs. Responsible for development of innovative DFT IP in collaboration with...
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30.08.2024
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Cisco ASIC Design Test Technical Leader United States, California, San Jose
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Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs. Responsible for development of innovative DFT IP in collaboration with...
17.09.2024
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Cisco ASIC STA Engineer United States, California, San Jose
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Bachelor’s degree in electrical or computer engineering (or other equivalent field) with 7+ years of related work experience. Experience with Integration for STA: including Hyperscale and hierarchical analysis with parasitic...
30.08.2024
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Cisco ASIC Reliability Engineer United States, California, San Jose
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Own reliability test plans for new products, including sample testing and full qualification prior to volume production release. Perform reliability evaluation of IC products, packages, and process technology with focus...
15.09.2024
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Cisco ASIC Engineer II Intern United States United States, California, San Jose
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Ability to manage multiple tasks and work toward long-term goals. Experience inestablishingand sustaining strong relationships with an extended team. Ability to work collaboratively across business groups. Excellent communication skills (verbal...
15.09.2024
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Cisco Physical Design Engineer United States, California, San Jose
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Perform full chip DRC/LVS/ERC/ANT checks, review and debug the issues, provide solutions and ensure signoff clean results. Work with block and top level implementation teams to understand physical aspects and...
12.06.2024
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Cisco ASIC Design Engineer United States, California, San Jose
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You will author design specifications and participate in micro-architecture specification reviews. Implement Verilog RTL to meet timing, performance, and power requirements. Contribute to full chip integration and timing methodology /...
Description:Full job details
Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs. Responsible for development of innovative DFT IP in collaboration with...
These jobs might be a good fit
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