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Senior Software Engineer Full jobs at Cisco in United States, San Francisco
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United States
State
San Francisco
364 jobs found
06.04.2025
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Cisco ASIC Engineer United States, California, San Jose
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The application window is expected to close on: 5/30/2025Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.Minimum Requirements:Bachelor’s degree...
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06.04.2025
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Cisco Software Engineer United States, California, San Francisco
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Design Scalable data pipelines for large semi-structured data using advanced distributed cloud data warehouse technologies. Build backend and data infrastructure that supports our need for fast data ingestion including customer...
06.04.2025
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Cisco Software Engineer United States, California, San Jose
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Bachelor’s degree in Computer Science, Computer Engineering, Electrical Engineering, or related degree and 5+ years of experience in an Engineering role or Master's degree with 3+ years of related experience....
06.04.2025
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Cisco Principal Mechanical Engineer United States, California, San Jose
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Lead architectural definition and drive new technology implementation in next- generation platforms. Develop innovative solutions to complex problems. Provide technical guidance and mentoring to team members. Lead failure analysis efforts...
06.04.2025
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Cisco Senior Mechanical Engineering Technical Leader United States, California, San Jose
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Provide leadership and problem-solving expertise for mechanical testing at a part or system level. Lead/mentor other engineers and convey technical guidance to resolve complex projects/issues. Architect, design, and deliver system...
06.04.2025
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Cisco Senior Machine Learning Engineer United States, California, San Francisco
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Design Scalable data pipelines for large semi-structured data using advanced distributed cloud data warehouse technologies. Build backend and data infrastructure that supports our need for fast data ingestion including customer...
06.04.2025
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Cisco Physical Design Lead Engineer United States, California, San Jose
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Lead chip-level PNR activities, from floor planning, bump and rdl planning, power grid design to clock planning, routing, and timing closure. Perform full chip DRC/LVS/ERC/ANT checks, review and debug the...
Description:Full job details
The application window is expected to close on: 5/30/2025Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.Minimum Requirements:Bachelor’s degree...
These jobs might be a good fit
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