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Armenia
Yerevan
6 jobs found
07.10.2025
C
Cisco ASIC Verification Technical Lead Armenia, Yerevan
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Responsible for thorough test planning and development of test benches to verify comprehensive Design-for-Test (DFT) architecture that supports ATE screening, in-system test, debug and diagnostics needs of the design. Work...
Description:
You will be in the Silicon One development organization as a senior DFT verification lead in Armenia. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive high-quality DFT verification.
Your Impact- Responsible for thorough test planning and development of test benches to verify comprehensive Design-for-Test (DFT) architecture that supports ATE screening, in-system test, debug and diagnostics needs of the design
- Work closely with the design/design-verification and PD teams to enable the integration and validation of the test logic in all phases of the implementation and post silicon validation flows.
- Work with the team on Innovative Hardware DFT & test strategy aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug methodologies and standards.
- Work with the team on DFT challenge identification, cross-functional solution brainstorming and implementation plan development, and lead junior engineers to deliver expected implementations on schedule.
- The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.
- Bachelor's or Master’s Degree in Electrical or Computer Engineering required with at least 10 years of experience.
- Prior experience in test planning based on complex design specification.
- Prior experience in testbench development using System Verilog.
- Debugging experience using DVE/Verdi.
- Scripting skills: Tcl, Python/Perl.
- UVM and advanced System Verilog knowledge.
- Knowledge about JTAG protocol, scan architecture, MBIST and boundary scan.
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08.09.2025
C
Cisco Physical Design Technical Leader Armenia, Yerevan
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Lead the team responsible for full-chip and block-level physical implementation, from RTL to GDSII and tape-out. Oversee all aspects of the physical design process, including synthesis, place and route, timing...
Description:
Your Impact
As a Physical Design Manager, you will play a key leadership role in Cisco’s Silicon One development, overseeing the full physical implementation process from RTL to GDSII and tape-out. You will drive the team responsible for block-level and full-chip design, ensuring that all aspects meet rigorous performance, area, and power requirements. In this role, you’ll collaborate cross-functionally with teams spanning frontend, IP, and tool vendors, both locally and globally, to deliver signoff-clean, next-generation networking chips. Beyond technical leadership, you’ll foster a culture of mentorship, learning, and innovation—enabling your team and yourself to grow and make a real-world impact.
What You'll Do
- Lead the team responsible for full-chip and block-level physical implementation, from RTL to GDSII and tape-out.
- Oversee all aspects of the physical design process, including synthesis, place and route, timing closure, and sign-off.
- Ensure all designs meet performance, area, and power requirements, and that handoffs between teams are seamless and timely.
- Collaborate closely with cross-functional teams to align on implementation challenges and solutions.
- Provide technical leadership, mentorship, and support to team members, empowering their growth and success.
- Engage in strategic planning and contribute ideas to optimize physical design methodologies and workflows.
Minimum Qualifications
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related field.
- 8+ years of experience in ASIC design and physical implementation, including verification.
- Deep expertise with deep submicron CMOS technologies.
- Extensive knowledge of the full design cycle from RTL to GDSII.
- Strong understanding of Static Timing Analysis, timing closure, and design constraints.
- Proven skills in block-level synthesis, place and route, and timing closure.
- Familiarity with industry-standard physical design and sign-off tools.
- Excellent verbal and written communication skills in English.
- Proven experience managing technical teams in a fast-paced environment.
Preferred Qualifications
- Direct experience with EM/IR and ESD analysis, including debugging and solution development.
- Proficiency in scripting languages such as Tcl, Python, or Shell to improve design flow efficiency.
- Experience collaborating with global teams and vendor partners.
- Demonstrated ability to mentor team members and foster a collaborative environment.
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27.07.2025
C
Cisco ASIC EM/IR Analysis Engineer Armenia, Yerevan
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Perform full-chip EM/IR analysis, debug issues, provide solutions, and ensure signoff clean results. Conduct voltage-aware STA at both full-chip and block levels, review and resolve issues to achieve timing closure....
Description:
What You'll Do
- Perform full-chip EM/IR analysis, debug issues, provide solutions, and ensure signoff clean results.
- Conduct voltage-aware STA at both full-chip and block levels, review and resolve issues to achieve timing closure.
- Implement full-chip and block-based ECOs for EM/IR violations, refining strategies to ensure seamless execution.
- Generate and implement manual ECOs for EM/IR challenges.
- Collaborate closely with block-level physical design teams to understand implementation challenges and ensure alignment.
- Perform full-chip and block-level ESD Resistance/CD analysis, debug issues, and ensure clean signoff results.
Minimum Qualifications
- Strong knowledge and expertise in EM/IR analysis, including debugging and developing effective solutions.
- 3+ years of experience working with deep submicron CMOS technologies.
- Solid understanding of the CMOS Digital Design Flow and its applications.
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related field.
Preferred Qualifications
- Comprehensive expertise of the full physical design cycle from RTL to GDSII.
- First-hand experience with EM/IR and ESD analysis.
- Proficiency in scripting languages such as Tcl, Python, or Shell to improve efficiency.
- Excellent verbal and written communication skills in English.
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08.07.2025
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Cisco Physical Verification Engineer Armenia, Yerevan
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Perform full-chip physical verification tasks, including DRC, LVS, ERC, and ANT checks, ensuring signoff-clean results. Debug and resolve physical verification issues at both block and chip levels, working closely with...
Description:
What You'll Do
- Perform full-chip physical verification tasks, including DRC, LVS, ERC, and ANT checks, ensuring signoff-clean results.
- Debug and resolve physical verification issues at both block and chip levels, working closely with implementation teams and IP developers.
- Collaborate with block and TOP-level implementation teams to provide feedback on physical design updates.
- Deploy and enhance physical verification flows and methodologies, including the development of custom checks for robust verification.
- Support block and chip-level teams in resolving local physical verification challenges.
MINIMUM QUALIFICATIONS
- 5+ years of experience in TOP-level physical verification, including debugging and providing solutions for DRC, LVS, ERC, and ANT issues.
- Strong expertise in deep submicron CMOS/FinFet technologies and experience with relevant processes.
- Solid understanding of physical verification and signoff methodologies.
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related field.
- Excellent verbal and written communication skills in English.
PREFERRED QUALIFICATIONS
- Comprehensive understanding of the full physical design cycle from RTL to GDSII.
- First hand experience with ASIC implementation and verification workflows.
- Proficiency in scripting languages such as Python, Tcl, or Shell for automation and efficiency improvements.
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11.06.2025
C
Cisco ASIC Technical Design Lead Engineer Armenia, Yerevan
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Participate and contribute to chip sensors architecture definition and discussions. Generate and verify different configurations of sensor to ASIC chip. Implement testbenches, run simulation and verification. Help define, evolve, and...
Description:
Responsibilities:
- Participate and contribute to chip sensors architecture definition and discussions.
- Generate and verify different configurations of sensor to ASIC chip
- Implement testbenches, run simulation and verification
- Help define, evolve, and support sensor integration in block and chip level.
- Collaborate with physical design and front end teams close design timing and place-and-route issues
- Triage, debug, and root cause simulation, software bring-up, and customer failures.
- BS/MS in Electrical Engineering or Computer Science
- 10+ years of experience in ASIC design
- Excellent Verilog/System Verilog programming skills.
- Knowledge of Silicon Lifetime Managements IP, their usage, verification specs
- Experience with simulators/synthesis/static timing constraints and tools
- Good understanding of verification methodologies and flow
- Strong interactive and waveform debug skills.
- Excellent English verbal and written communication skills.
- Self-motivated, able to work independently or as a team player
- Experience in block level synthesis, place and route, timing closure is ideal.
- Scripting experience (Python, Perl, TCL, shell programming) highly valuable.
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28.04.2025
C
Cisco ASIC Physical Design Engineer Armenia, Yerevan
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Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes. Option to also do...
Description:
The application window is expected to close on: May 9, 2025.
Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.
This role requires being onsite in San Jose, CA 4+ days/week.
Your Impact
You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock groups, exceptions, and clock exclusivity. Proficient in industry-standard SDC/STA tools and scripting for automation, you excel at identifying and resolving timing issues across all design levels. You will collaborate with Front-end and Back-end teams to understand chip architecture and guide them in refining design and timing constraints for seamless physical design closure. As part of this team, you’ll contribute to developing next-generation networking chips.
Responsibilities include:
- Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes.
- Option to also do block level RTL design or block or top-level IP integration.
- Helping develop efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC changes back to block level.
- Helping develop and apply methodology to ensure correctness and quality of SDCs as early as possible in design cycle.
- Reviewing block level SDCs and clocking diagrams and mentor other RTL design owners on SDC development.
- Leading the fullchip clocking design including diagrams and related documentation.
Minimum Qualifications:
- Bachelor’s Degree in Electrical or Computer Engineering with 12+ years of ASIC or related experience or Master’s Degree in Electrical or Computer Engineering with 8+ years of ASIC or related experience.
- Experience with microarchitecture and RTL implementation.
- Experience with digital design concepts (eg. clocking and async boundaries).
- Experience with block/full chip SDC development in functional and test modes.
- Experience with synthesis tools (eg. Synopsys DC/DCG/FC) and Verilog/System Verilog programming.
Preferred Qualifications:
- Experience in Static Timing Analysis.
- Experience with constraint analyzer tools such as Fishtail/TCM (Timing Constraint Manager from Synopsys) and CCD (Conformal Constraint Designer from Cadence).
- Experience with Spyglass CDC and glitch analysis.
- Experience with STA tools such as PrimeTime/Tempus.
- Experience with scripting languages such as Python, Perl, or TCL.
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Responsible for thorough test planning and development of test benches to verify comprehensive Design-for-Test (DFT) architecture that supports ATE screening, in-system test, debug and diagnostics needs of the design. Work...
Description:
You will be in the Silicon One development organization as a senior DFT verification lead in Armenia. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive high-quality DFT verification.
Your Impact- Responsible for thorough test planning and development of test benches to verify comprehensive Design-for-Test (DFT) architecture that supports ATE screening, in-system test, debug and diagnostics needs of the design
- Work closely with the design/design-verification and PD teams to enable the integration and validation of the test logic in all phases of the implementation and post silicon validation flows.
- Work with the team on Innovative Hardware DFT & test strategy aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug methodologies and standards.
- Work with the team on DFT challenge identification, cross-functional solution brainstorming and implementation plan development, and lead junior engineers to deliver expected implementations on schedule.
- The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.
- Bachelor's or Master’s Degree in Electrical or Computer Engineering required with at least 10 years of experience.
- Prior experience in test planning based on complex design specification.
- Prior experience in testbench development using System Verilog.
- Debugging experience using DVE/Verdi.
- Scripting skills: Tcl, Python/Perl.
- UVM and advanced System Verilog knowledge.
- Knowledge about JTAG protocol, scan architecture, MBIST and boundary scan.
Show more
These jobs might be a good fit
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