Senior Devops Platform Engineer jobs at Broadcom in United States, San Jose

As a member of the VCF Automation team, you will be building software solutions that provide our customers self-service consumption of Kubernetes and cloud infrastructure resources “as a Service” while maintaining control, security, and compliance. You will collaborate with peers in the team and cross-functional organizations to understand requirements and implement solutions.

You will become an integral part of the team:

• Within the first month of employment, you will become familiar with the product features, architecture, and development process. You will ramp up quickly and be able to commit code that addresses an issue or enhances an existing feature.

• Within 3 months of employment, you will begin implementing a product feature with your team.

• Within 6 months of employment, you will be able to support our existing customers, work on new features, and propose improvements to the product.

• Within the first year of employment, you will ship code that customers are depending on to run their businesses!

• Join a talented development team capable of working across functional and geographic boundaries to deliver high-quality features and enhancements to customers.

• Use and learn popular, modern technologies and methods to construct and enhance an open-source, Go-based Terraform provider.

• Work with senior members of the team to deliver new capabilities to customers.

• Engage with the open-source community and development process while adhering to the quality and security standards required by the VCF platform.

• Prioritize the success of existing and potential customers by providing prompt consultation and support, driving open issues to conclusion with urgency and to all stakeholders’ satisfaction.

You will be joining the VCF Automation team responsible for delivering the open-source Terraform provider that enables Terraform users to interface with VCF Automation. You will work in-person, daily, from a designated VCF office in the United States, and will collaborate with engineers and cross-functional team members locally, across the country and around the globe.

• Bachelors OR Masters in Computer Science or Engineering plus a minimum of 8 years/6 years related industry experience,

• Significant experience developing Go-based applications

• Experience contributing to and interacting with open-source projects/communities

• Familiarity with Terraform and/or Kubernetes

• Awareness of VMware Cloud Foundation Automation and its predecessors—VMware Aria Automation and VMware Cloud Director

• Knowledge of tools like GitHub, Maven, and Jenkins

• Experience in effective code reviews and cross-functional team work with other engineering dependencies, OSS projects, product and release management

• Understanding of enterprise SDLC processes and willingness to engage with these throughout the lifecycle of your work

• Ability to work from the VCF office in Burlington, MA, or Palo Alto, CA, office five days/week

• Must have legal authorization to work in the US

As a member of the VCF Automation team, you will be building software solutions that provide our customers self-service consumption of Kubernetes and cloud infrastructure resources “as a Service” while maintaining control, security, and compliance. You will collaborate with peers in the team and cross-functional organizations to understand requirements and implement solutions.

You will become an integral part of the team:

• Within the first month of employment, you will become familiar with the product features, architecture, and development process. You will ramp up quickly and be able to commit code that addresses an issue or enhances an existing feature.

• Within 3 months of employment, you will begin implementing a product feature with your team.

• Within 6 months of employment, you will be able to support our existing customers, work on new features, and propose improvements to the product.

• Within the first year of employment, you will ship code that customers are depending on to run their businesses!

• Join a talented development team capable of working across functional and geographic boundaries to deliver high-quality features and enhancements to customers.

• Use and learn popular, modern technologies and methods to construct and enhance Java-based microservices running in a containerized environment.

• Work with senior members of the team to deliver new capabilities to customers.

• Engage with an enterprise SDLC process and maintain quality and security standards in order to ship with the VCF platform.

• Prioritize the success of existing and potential customers by providing prompt consultation and support, driving open issues to conclusion with urgency and to all stakeholders’ satisfaction.

You will be joining the VCF Automation team responsible for delivering API-driven backend services that power private cloud infrastructure and application automation at scale. You will work in-person, daily, from a designated VCF office in the United States, and will collaborate with engineers and cross-functional team members locally, across the country and around the globe.

• Bachelors OR Masters in Computer Science or Engineering plus a minimum of 8 years/6 years related industry experience,

• Deep experience developing Java-based enterprise applications for on-premise customers; experience with Spring and Spring Boot a plus

• Familiarity with Kubernetes, containerization, and virtualization

• Knowledge of tools like GitHub, Maven, and Jenkins

• Experience in effective code reviews and cross-functional team work with other engineering dependencies, OSS projects, product and release management

• Understanding of enterprise SDLC processes and willingness to engage with these throughout the lifecycle of your work

• Ability to work from the VCF office in Burlington, MA, or Palo Alto, CA, office five days/week

• Must have legal authorization to work in the US

RESPONSIBILITIES:

• Overall design responsibility for ASIC package designs, including aspects of signal integrity, power integrity, manufacturability, reliability, and thermal, in partnership with our experienced team of package engineering experts.
• Package Design of critical structures for SerDes, ADC/DAC, DDR, etc.
• Schedule, prioritize, & track your work across 2+ projects simultaneously
• General flip-chip BGA package design & engineering
• Project management and customer interface for your design projects
• Contribute to efficiency improvements for the design team, through processdevelopment/improvement,automation, documentation, etc.
• Physical design (layout) is a foundational responsibility in this role

EDUCATION/EXPERIENCE & REQUIREMENTS:

• BSEE or similar field and 12+ years’ experience in flip-chip-BGA package design, including high-speed SerDes or MSEE or similar field and 10+ years’ work experience
• Knowledge of package-level signal integrity and power integrity, to apply to package designs
• Cadence APD (allegro package designer) experience is preferred. Equivalent tool is OK.
• Cooperate with our world-wide team (multiple time zones), including co-design with internal team members and external (Vendor) designers
• Self-management and organization skills
• Preferred candidates will also have 1 or more years experience with Cadence SKILL for Allegro, or similar design-automation coding experience and interest

OTHER REQUIREMENTS

• This job requires working on-site at the Broadcom office, 5-days a week. This is not a remote-work position

Compensation and Benefits

The annual base salary range for this position is $141,300 - $226,000.

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Compensation and Benefits

The annual base salary range for this position is $141,000 - $225,000

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Job Description:

• This opening is for working on chips that enable Physical Layer Products for High Speed Optical Communication.

• architect block level design specifications from the marketing requirements and/or system requirements

• prepare detailed design document, timing constraint file

• RTL coding, Lint checks, CDC, Synthesis, Equivalency checking, STA, RTL/gate level simulations & silicon debug

• Scripting for various IC design tasks such as STA, equivalency checks, test bench, simulations, synthesis, etc.

• prepare block level resource requirements & development schedule

• generate verification & test plans for design validation

• Perform design tradeoff analysis – leakage, dynamic power, die size, schedule, resource, priority, etc.

• silicon bring up and validation, ATE program bring up

Job Requirement:

• B.S degree in EE or computer Engineering. Minimum of 12 years of work experience with direct related technical skill

• M.S degree in EE or Computer Engineering with 10+ years of work experience, or Ph.D with 7+ years of work experience

• Good knowledge of ARM subsystem

• Good knowledge of high speed digital circuit design.

• Good knowledge of digitalupsampling/downsampling

• Good knowledge of10G/100G/200G/400G/800GEthernet and OTN network.

• Good knowledge on FEC (Forward Error Correction) design.

• Good knowledge of digital signal processing and error correction code is a plus

• Strong analytical and problem solving skills as well as hands-on lab debugging experiences

• Good knowledge of RTL simulation and synthesis.

• In-depth knowledge for design for low power and design for test and design for manufacturing.

• Good Knowledge in languages relevant to the ASIC development process including Verilog, VHDL, Unix/Perl Scripting or Python, and C.

• Self-motivated, excellent communication skills and ability to excel in a team environment.

• Good organization skills, able to follow through & bring issue to closure

• Understand the entire IC development flow & procedure including silicon volume production qualification requirements & procedures

• Enthusiastic & enjoy IC development works

• Be able to work with teams at remote locations with different time zone.

Compensation and Benefits

The annual base salary range for this position is$141,000 -$225,000

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Job Duties and Responsibilities.

• Work with a wide variety of businesses inside Broadcom to understand current and future SCM requirements.

• Work with our senior devops team to design, architect and deliver full CI pipeline solutions.

• Deliver simple, scalable solutions.

• Continue learning about the latest technologies in the field and learn when, how and whys of deploying them.

• Communicate clearly with the team as well as internal customers.

• Monitor services and platforms, providing solutions and/or improvements.

Essential Requirements

• Undergraduatedegree in computer science, IT, software engineering, or similar

• Strongcommunication skills (verbal and written).

• Minimumof 12 years of experience in Software Engineering roles as DevOps Platform engineer.

• Expertin maintaining and managing software build infrastructure. (GitHub Actions, Jenkins, etc.)

• Expertin container technologies such as Docker and Kubernetes

• Expertin IaC technologies such as Helm, Packer, and Terraform.

• Expertexperience creating, maintaining, and supporting CI/CD pipelines.

• Expertexperience in version control and source control management (GitHub, Gerrit, Gitlab, Perforce)

• Expertin deploying, managing, and maintaining at least 2 of the following SCM toolchain such as Jenkins, Artifactory, SonarQube, Twistlock, Blackduck, Coverity

• Strongunderstanding of programming principles, structure, and Versioning.

• Experiencein scripting languages such as Python, Bash, and PowerShell, and others are nice to have.

• Experiencewith system management technologies such as Puppet, Ansible, Salt, or Chef.

• Experienceand knowledge of Microsoft and/or Linux system administration and networking.

• Experiencein managing a VMware-based virtualization environment or similar.

• Knowledgeof test-driven development, software configuration management, and automated testing.

Highly Desirable Requirements

• Experienceoperating in a fast paced environment..

• Experiencein managing CI/CD pipelines for a mixed set of software assets.

Compensation and Benefits

The annual base salary range for this position is $103,000 - $182,000.

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Key Responsibilities:

• Implement and verify DFT methodologies specifically for HBM, DDR and SerDes designs.
• Collaborate with design and architecture teams to identify and define critical testability requirements.
• Utilize advanced simulation tools and methodologies to thoroughly verify DFT implementations.
• Analyze DFT-related data and provide insights for continuous design improvements.
• Document verification processes, results, and best practices to enhance team knowledge and efficiency.
• Stay updated with the latest trends and technologies in DFT, HBM, and SerDes to drive innovation within the team.
• Working closely with STA and DI Engineers design closure for test
• Generating, Verifying & Debugging Test vectors before tape release.
• Validating & Debugging Test vectors on ATE during the silicon bring up phase
• Assisting with silicon failure analysis, diagnostics & yield improvement efforts
• Interfacing with the customers, physical design and testengineering/manufacturingteams located globally
• Working closely with I/P DFT engineers & other stakeholders
• Debugging customer returned parts on the ATE
• Innovating newer DFT solutions to solve testability problems in 3nm IPs & beyond
• Automating DFT & Test Vector Generation flows

Skills/Experience:

• Strong DFT background (such as Analog DFT, MBIST, IEEE1687 and others)
• Proven experience in DFT verification, particularly with HBM, DDR, PCIE and other SerDes IPs.
• Understanding of DFT methodologies, including scan, BIST, and ATPG.
• Proficiency in simulation tools and scripting languages (e.g., Perl, Python, TCL and ruby).
• Excellent analytical and problem-solving skills.
• Strong communication and teamwork abilities.
• The ability to work in a multi-disciplined, cross-department environment
• Solid knowledge in analog and digital circuit design, and device physics fundamentals
• Excellent problem solving, debug , root cause analysis and communication skills
• Experience working on ATE is a plus
• Familiarity with BIST logic for array and link testing is a plus
• Knowledge of AHB/APB/AXI buses is a plus

Education & Experience:

• Bachelors inElectrical/Electronic/ComputerEngineering and 8+ years of relevant industry experience or Masters Degree inElectrical/Electronic/ComputerEngineering and 6+ years of relevant industry experience

Compensation and Benefits

The annual base salary range for this position is $107,000 - $190,000.

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.