Advanced Package Technology Engineer jobs at Broadcom in United States, Fort Collins
Broadcom Design Automation Engineer United States, Colorado, Fort Collins
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Responsibilities:
Develop and support design automation flows for ASIC products and associated IPs.
This role involves
- Physical verification runset support and development
- Providing guidance to designers for fixing issues arising from LVS, ERC and DRC errors
- Design automation flow support and development
- Integration of flows and checks into design cockpits
- Regression testing of flows and verification checks
- Parasitic extraction and simulation, abstract and LEF/DEF generation, LVS/ERC checks
- Conducting design reviews & creating slides and other associated documentation
- Assisting with integration of IP into SOCs and creating guidelines
Knowledge and Experience required:
- A good understanding of IP & ASIC design methodologies
- Extensive experience with EDA DRC/LVS support
- Knowledge of verification languages TVF, SVRF, PXL
- Knowledge of various environments and languages – Shell Scripting, Linux development environment, PERL, RUBY, TCL, SKILL/SKILL++, C, C++
- Familiarity with advanced semiconductor process technologies like 3nm, 5nm, 7nm; Design experience is a plus.
- Experience implementing design automation using Cadence Virtuoso for Analog and Mixed-Signal IP development
- Familiarity with software & design data management systems like git, DesignSync
- Familiarity with common EDA data formats like LEF/DEF, OASIS, openAccess, SPICE/SPECTRE
- Knowledge of various EDA offerings from major EDA suppliers in semiconductor industry for IP and chip design
- The ideal candidate will have wide-ranging experience, with a demonstrated ability to rely on thorough understanding of engineering fundamentals
- The ideal candidate will also have a demonstrated ability to clearly present their work to designers and to non-experts as well
- Working in team environment is a must and everyday interaction with internal customers is part of the job
Education:
- Bachelor’s degree in Electrical Engineering and 12+ years of related experience or Master’s degree and 10+ years of related experience, or PhD and 7+ years of related experience.
Compensation and Benefits
The annual base salary range for this position is $141,000 - $225,000
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
These jobs might be a good fit
Broadcom Firmware Development Engineer United States, Colorado, Fort Collins
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Job Description:
Job Requirements:
A Bachelor’s Degree in Electrical and Electronic Engineering, Computer Science, or equivalent and 8+ years related experience.
Strong cross platform C/C++ programming experience.
Experience developing embedded firmware with direct low level HW interactions.
Experience with scripting languages (Ruby, Perl, bash etc.).
Experience working in Verilog (i.e SystemVerilog, Verilog, VHDL) test fixtures
Desired:
Knowledge of embedded firmware, real-time operating system (RTOS), and HW/SW interactions.
Experience with hardware/software debugging.
Experience with GIT, Gerrit, and Jenkins
Compensation and Benefits
The annual base salary range for this position is $107,000 - $190,000.
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
These jobs might be a good fit
Broadcom Design Automation Engineer United States, Colorado, Fort Collins
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Responsibilities:
Develop and support design automation flows for ASIC products and associated IPs.
This role involves
- Design automation flow support and development
- Parasitic extraction and simulation, abstract and LEF/DEF generation, LVS/ERC checks
- Physical verification runset support and development
- Integration of flows and checks into design cockpits
- Regression testing of flows and verification checks
- Conducting design reviews & creating slides and other associated documentation
- Assisting with integration of IP into SOCs and creating guidelines
- Providing guidance to designers for fixing issues arising from LVS, ERC and LPE errors
Knowledge and Experience required:
- A good understanding of IP & ASIC design methodologies
- Experience implementing design automation using Cadence Virtuoso for Analog and Mixed-Signal IP development
- Knowledge of various environments and languages – Shell Scripting, Linux development environment, PERL, RUBY, TCL, SKILL/SKILL++, C, C++
- Familiarity with advanced semiconductor process technologies like 3nm, 5nm, 7nm; Design experience is a plus.
- Familiarity with software & design data management systems like git, DesignSync
- Familiarity with common EDA data formats like LEF/DEF, OASIS, openAccess, SPICE/SPECTRE
- Familiarity with EDA verification languages TVF, SVRF, PXL
- Knowledge of various EDA offerings from major EDA suppliers in semiconductor industry for IP and chip design
- The ideal candidate will have wide-ranging experience, with a demonstrated ability to rely on thorough understanding of engineering fundamentals
- The ideal candidate will also have a demonstrated ability to clearly present their work to designers and to non-experts as well
- Working in team environment is a must and everyday interaction with internal customers is part of the job
Education:
- Bachelor’s degree in Electrical Engineering and 8+ years of related experienc or Master’s degree and 6+ years of related experience, or PhD and 3+ years of related experience.
Compensation and Benefits
The annual base salary range for this position is $107,000 - $190,000.
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
These jobs might be a good fit
Broadcom Serdes / High Speed IO DFT engineer United States, Colorado, Fort Collins
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Job Description:
SerDes DFT & Test Engineer
Key Responsibilities:
Implement and verify DFT methodologies for SerDes IP.
Collaborate with design and architecture teams to identify and define critical testability requirements.
Utilize advanced simulation tools and methodologies to thoroughly verify DFT implementations.
Analyze DFT-related data and provide insights for continuous design improvements.
Document verification processes, results, and best practices to enhance team knowledge and efficiency.
Stay updated with the latest trends and technologies in DFT to drive innovation within the team.
Working closely with STA and DI Engineers design closure for the test.
Generating, Verifying & Debugging Test vectors before tape release.
Validating & Debugging Test vectors on ATE during the silicon bring up phase.
Assisting with silicon failure analysis, diagnostics & yield improvement efforts.
Interfacing with the customers, physical design and testengineering/manufacturingteams spanning multiple geographies.
Working closely with I/P DFT engineers & other stakeholders.
Debugging customers returned parts on the ATE.
Automating DFT & Test Vector Generation flows
Skills/Experience:
Good understanding of Mixed Signal IPs, Digital and Analog logic.
Strong DFT background (such as Analog DFT, MBIST, IEEE1687 and others)
Proven experience in DFT verification with detailed understanding of Serdes IP architecture, specifications.
Understanding of DFT methodologies, including scan, BIST, and ATPG.
Proficiency in simulation tools and scripting languages (e.g., Perl, Python, TCL and ruby).
Strong communication and teamwork abilities.
The ability to work in a multi-disciplined, cross-functional worldwide team environment.
Solid knowledge in analog and digital circuit design, and device physics fundamentals.
Excellent problem solving, debug , root cause analysis and communication skills.
Experience working on ATE is a plus.
Familiarity with BIST logic for array and link testing.
Knowledge of AHB/APB/AXI buses & Protocols such as PCIe, JESD, Ethernet are a plus.
Education & Experience:
Bachelors inElectrical/Electronic/ComputerEngineering and 15+ years of relevant industry experience or Masters Degree inElectrical/Electronic/ComputerEngineering and 13+ years of relevant industry experience
Compensation and Benefits
The annual base salary range for this position is $146,000 - $234,000.
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
These jobs might be a good fit
Broadcom Advanced Package Technology Engineer United States, Colorado, Fort Collins
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Job Description:
Compensation and Benefits
The annual base salary range for this position is $119,000 - $190,000
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
These jobs might be a good fit
Broadcom Package Design Engineer United States, Colorado, Fort Collins
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RESPONSIBILITIES:
2 or more years experience with Cadence APD, SiP, or equivalent package layout CAD tool (3 or more years is preferred)
Package Design of critical structures for SerDes, ADC/DAC, DDR, etc.
Schedule, prioritize, & track your work across 2+ projects simultaneously
General flip-chip BGA package design & engineering
Contribute to efficiency improvements for the design group
EDUCATION/EXPERIENCE & REQUIREMENTS:
BSEE or similar field and 8+ years’ experience in flip-chip-BGA package design, including high-speed SerDes or MSEE or similar field and 6+ years’ experience in flip-chip-BGA package design, including high-speed SerDes
Knowledge of package-level signal integrity and power integrity, to apply to package designs
Cadence APD (allegro package designer) experience is preferred. Equivalent tool is OK.
Self-management and organization skills
Compensation and Benefits
The annual base salary range for this position is $107,000 - $190,000.
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
These jobs might be a good fit
Broadcom Package Design Engineer United States, Colorado, Fort Collins
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RESPONSIBILITIES:
or more years experience with Cadence APD, SiP, or equivalent package layout CAD tool (3 or more years is preferred)
Package Design of critical structures for SerDes, ADC/DAC, DDR, etc.
Schedule, prioritize, & track your work across 2+ projects simultaneously
General flip-chip BGA package design & engineering
Contribute to efficiency improvements for the design group
EDUCATION/EXPERIENCE & REQUIREMENTS:
BSEE or similar field and 8+ years’ experience in flip-chip-BGA package design, including high-speed SerDes or MSEE or similar field and 6+ years’ experience in flip-chip-BGA package design, including high-speed SerDes
Knowledge of package-level signal integrity and power integrity, to apply to package designs
Cadence APD (allegro package designer) experience is preferred. Equivalent tool is OK.
Self-management and organization skills
Compensation and Benefits
The annual base salary range for this position is $107,000 - $190,000.
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
These jobs might be a good fit
Share
Responsibilities:
Develop and support design automation flows for ASIC products and associated IPs.
This role involves
- Physical verification runset support and development
- Providing guidance to designers for fixing issues arising from LVS, ERC and DRC errors
- Design automation flow support and development
- Integration of flows and checks into design cockpits
- Regression testing of flows and verification checks
- Parasitic extraction and simulation, abstract and LEF/DEF generation, LVS/ERC checks
- Conducting design reviews & creating slides and other associated documentation
- Assisting with integration of IP into SOCs and creating guidelines
Knowledge and Experience required:
- A good understanding of IP & ASIC design methodologies
- Extensive experience with EDA DRC/LVS support
- Knowledge of verification languages TVF, SVRF, PXL
- Knowledge of various environments and languages – Shell Scripting, Linux development environment, PERL, RUBY, TCL, SKILL/SKILL++, C, C++
- Familiarity with advanced semiconductor process technologies like 3nm, 5nm, 7nm; Design experience is a plus.
- Experience implementing design automation using Cadence Virtuoso for Analog and Mixed-Signal IP development
- Familiarity with software & design data management systems like git, DesignSync
- Familiarity with common EDA data formats like LEF/DEF, OASIS, openAccess, SPICE/SPECTRE
- Knowledge of various EDA offerings from major EDA suppliers in semiconductor industry for IP and chip design
- The ideal candidate will have wide-ranging experience, with a demonstrated ability to rely on thorough understanding of engineering fundamentals
- The ideal candidate will also have a demonstrated ability to clearly present their work to designers and to non-experts as well
- Working in team environment is a must and everyday interaction with internal customers is part of the job
Education:
- Bachelor’s degree in Electrical Engineering and 12+ years of related experience or Master’s degree and 10+ years of related experience, or PhD and 7+ years of related experience.
Compensation and Benefits
The annual base salary range for this position is $141,000 - $225,000
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
These jobs might be a good fit
