Automated Gui Testing Lead jobs at Arm in United States, Austin

Key Responsibilities:

· Develop and maintain video codec drivers.

· Optimize video codec performance and ensure correctness.

· Collaborate with team members to integrate video codec drivers into the broader software stack.

· Conduct thorough testing and debugging to ensure reliability and performance.

· Engage in device emulation to simulate and troubleshoot real-world scenarios.

· Contribute to related open-source projects and work with their communities.

· Support partners as they rely on our products.

· Help Arm grow and be better and be part of a wider team

Required Skills and Experience:

• A bachelor's degree in computer science, electrical engineering, or related fields.
• Strong knowledge of video codecs, computer graphics, rendering, image processing and related technologies.
• High proficiency in C programming language.
• Extensive experience with Linux operating systems.
• Low-level programming experience and familiarity with hardware-software interactions.

‘Nice to Have’ Skills and Experience:

• Experience in testing and device emulation.
• Familiarity with open-source development and contributions.
• Working knowledge of SCMS tools like Git and related infrastructure such as GitHub, GitLab, Gerrit etc.
• Familiarity with ARM architecture.
• Experience with other programming languages such as C++, Rust or Python.
• Knowledge of multimedia frameworks and libraries.
• Experience with non-Linux kernel based operating systems and their driver models

• Lead a team of SPT engineers accountable for productization of high performance SOC, including all NPI ATE/SLT activities
• Develop/deliver manufacturing test solutions for high performance SOCs
• Work with operations team on ATE/SLT bring-up, characterization and productization
• Drive first silicon bring-up on ATE and SLT, reporting daily progress across the organization
• Up to 20% travel within US and internationally for company and partner meetings

• Proven experience leading NPI of high-performance SoC’s
• Broad understanding of DFT (Scan, MBIST, PHY BIST, etc), ATE, SLT, silicon fabrication process, packaging, etc
• Silicon data analysis including performance/yield sensitivities within foundry, assembly, and test processes
• Demonstrated ability in product/test engineering, including manufacturing test, yield improvement, silicon characterization and reliability qualification

• Proficient in data analysis techniques and tools, such as excel, Tableau, JMP, etc
• Experience with Streaming Scan Network (SSN), IJTAG, scan diagnostics, FI/FA techniques, Q&R concepts, etc
• Expert knowledge of SOC concepts such as: DVFS/SVC, sensor calibration, FMAX/VMIN determination, OTP/eFuse allocation/management, logic harvesting, etc
• Productization of 2.5D and 3D System-in-Package (SiP), including multi-SKU product definition

The Power Architecture and Attainment Lead role responsible for leading the delivery of SOC execution to meet product specific critical metrics. This work includes power budgeting, use-case analysis, estimation, and optimization for high-volume, sophisticated, SoC platforms on groundbreaking technology nodes across multiple market segments including IoT, AI/ML, compute, automotive, and server.

We are seeking strong technical leadership, with ability to develop accurate project plans involving multiple teams.

• Lead SoC power optimization for high-volume platforms, ensuring efficiency and performance across IoT, AI/ML, compute, automotive, and server markets.
• Expertise in RTL and Netlist based power analysis flows with good understanding of SoC physical design flows and simulation/emulation flows.
• Knowledge of ASIC design dependencies on power efficiency including technology node, mixed Vt design, standard cell and memory library selection, voltage and power domain partitioning.
• Proven experience driving multiple projects and supporting junior engineers.
• Appreciation of software use-cases, benchmarks, and workloads and how they interact with hardware low power features like clock and power gating, voltage/frequency scaling, memory/logic retention.
• Excellent presentation, interpersonal and communication skills. Able to present technical content inside and outside of Arm.

• Experience using tools for power analysis, power delivery and signoff. (e.g. PowerPro, PowerArtist, PrimePower, Redhawk, etc)
• Experience running simulation/emulation tools. (e.g. VCS, Questasim, Incisive, Veloce Strato, Palladium, Zebu, etc)
• Python for automation and modeling.
• SoC use-case power budget decomposition to IP power budget.
• Experience with correlation between pre and post silicon power.

You will join a highly focused group to create, learn, define and lead.

• Strong understanding of electronics and embedded compute systems.
• Familiarity with different IC packaging technologies and their impact on PCB design to ensure seamless integration of SoCs, ensuring proper signal routing and power delivery.
• Experience of collaborating with chip packaging teams. Ability to influence and drive SoC device pin-outs for cost optimization, routing feasibility and layer trade-off analysis.
• Detailed knowledge of high-speed design and interface standards (e.g. PCIe and DDR memory technologies). You'll analyze and optimize signal paths to ensure signal quality, minimize noise, and prevent signal degradation, especially at high speeds.
• Expertise in escape routing analysis of high density SoC's and able to provide estimates of the IO count that can be routed with a particular stack-up and design rule set.
• Extensive knowledge of Signal and Power Integrity analysis techniques from both board design and chip packaging perspectives.
• Understanding of the PCB fabrication process (PTH and HDI), stackup/VIA topologies and substrate materials. Ability to collaborate with PCB fabricators and CEMs.
• Proficiency in the use of EDA tools, specifically Cadence Allegro PCB suite and OrCAD CIS.
• Good communication and interpersonal skills. Positive can-do attitude and attention to detail.

The following skills are not essential, but experience in any of the following areas would enhance the application:

• Experience in using Signal Integrity tools from ANSYS, Siemens EDA etc.
• Experience of design automation and scripting.
• Enjoy collaborating and working in across geographies with multiple teams.

As a Staff Software Engineer- QA Lead on our IAS Networking team, you will be leading all validation and testing aspects which includes:

• Leading design and development of test cases and sample applications to ensure and demonstrate high quality real use cases on Arm platform.
• Work with open-source communities and key partners across the globe to build and maintain component and system level test applications as well as automate CI/CD pipelines.

Candidate should have master’s/bachelor's degree in computer science or an equivalent STEM degree or equivalent experience in the industry. In addition, candidate should:

• Proficient in C/C++/Python and scripting languages with at least 10 years of experience in leading software validation, test automation and benchmarking.
• Knowledgeable about standard testing practices for testing multi-core and multi-threaded applications and be an expert at identifying and stressing corner cases and boundary conditions.
• Experience in distributed version control systems, such as Git.
• Adept at data collection and presenting easily digestible reports using clear and effective communication skills.

• Familiar with open-source software contribution process and test pipelines.
• Experience with testing networking software stack components such as RoCE, OpenMPI, OneCCL, etc. used by AI applications.
• Experienced in crafting test and performance benchmarking apps for data plane software based upon DPDK, VPP, Snort, etc.
• Experience of building distributed test setup, using containers and pods, and testing with software and hardware traffic generators such as IXIA.