Principal Cpu Architect jobs at Arm in India, Bengaluru

Responsibilities

• As a creative design engineer with a knowledge of subsystems and SoCs you will be part team developing Subsystems & SoCs.
• You will work with Architects to capture the requirements and develop Micro-architecture specifications for one or more SOC areas such as Power Management, Boot, Debug, Clocks, Resets, DDR, RAS, Security, Access Control, Die to Die etc.
• Key responsibilities will include writing micro-architecture and work with Design team to deliver high quality RTL.
• Collaborate with verification and Validation team to review test plans, and help debug design issues. Closely work with the Power and Performance analysis team to evaluate and improve Subsystem/SOC PPA.
• Contribute to developing and improving the design methodologies.
• Guide and support other members of the team for overall Program success. Balance other opportunities such as working with Project Management on activities, plans, and schedules

Required Skills and Experience:

• Bachelors or Master’s degree or equivalent experience in Electronics/Electrical Engineering.
• Experience of 8+ years working in design of complex compute subsystems or SoCs
• Expertise in developing Micro-architecture and Design specifications for the SoC Infrastructure areas such as Power Management, Boot, Debug, Clocks, Resets, DDR, RAS, Security, Access Control, Die to Die etc.
• Solid understanding of digital hardware design and Verilog HDL. Experience in development and Tapeout of Complex SoC and RTL Development.
• Experience leading and developing RTL for Subsystems or SoCs.
• Conversant with Lint, CDC and RDC flows.
• Good communication (written, verbal, presentations) skills.
• Experience with Perl, Python or other scripting language

Desired Skills and Experience:

• Experience with ARM-based designs and/or ARM System Architectures
• Experience developing subsystems for PCIe, LPDDR, HBM, UCIe, Ethernet
• Experience with SystemVerilog and verification methodologies – UVM/OVM
• Experience leading small teams or projects
• Experience or knowledge in the following areas
• Synthesis and timing analysis
• Static design checks, including CDC, RDC, X-Propagation, Linting
• Power management techniques
• DFT and physical implementation

As a Security Engineer – Fuzzing Specialist, you will own and evolve our coverage-guided fuzzing program. Your mission is to uncover hard-to-reach security flaws before attackers do, drive fixes to closure, and help product teams to embrace dynamic testing like fuzzing. You’ll scout for new attack surfaces, craft high-performance fuzzing harnesses, and design custom sanitisers that push the state of the art. Success means measurable coverage gains, actionable crash reports, and products that ship with provable resilience.

• Map & prioritise fuzzing surfaces across services, libraries, APIs, and protocols; maintain a living risk-based roadmap.
• Design, build, and extend fuzzing harnesses (libFuzzer, AFL++, Honggfuzz, etc.) that improve code-path exploration and minimise false positives.
• Continuously improve coverage by growing seed corpus, deploying targeted mutation strategies, and integrating new instrumentation techniques.
• Automate crash triage & root-cause analysis; distinguish exploitable vulnerabilities from benign faults and drive CVE-level findings to remediation.
• Develop custom sanitisers to expose classes of bugs traditional fuzzing misses.
• Validate fixes & guard against regressions through differential fuzzing and regression corpora.
• Assess external disclosures (bug bounties, supply-chain advisories) to determine fuzzing detectability and refine harnesses when gaps are found.
• Document, report, and share insights — from coverage metrics to post-mortems to create data-driven security.

• 1+ years in application or product security with a deep focus on coverage-guided fuzzing.
• Hands-on expertise with at least one modern fuzzing framework (e.g., libFuzzer, AFL++, Honggfuzz).
• Proficient in C/C++ plus strong scripting ability in Python for automation.
• Solid understanding of memory-safety vulnerabilities, undefined behaviour, sanitisers, and compiler instrumentation.
• Demonstrated ability to triage crashes using debuggers, profilers, and reverse-engineering tools (gdb/lldb, IDA/Ghidra).
• Excellent written communication for documenting findings and influencing engineering teams.

• Contributions to open-source fuzzing tools, sanitisers, or security research publications.
• Knowledge of distributed fuzzing at scale (GCP/AWS, Kubernetes, or bare-metal clusters).
• Familiarity with kernel, embedded, or firmware fuzzing (e.g., Syzkaller, QEMU-based harnesses).
• Background in reverse engineering, static analysis or symbolic execution.
• Experience integrating fuzzing into CI/CD pipelines and tracking coverage metrics.

• Synthesis, Physical design and implementation of CPU and GPU cores, system interconnect and other ARM IP, SoC
• Analyze design timing, area and power to help improve the quality of ARM IP
• Develop and deploy new methodologies to improve implementation efficiency and results
• Support and develop detailed implementation analysis and data-mining methodologies.
• Work with implementation and physical IP RTL design teams to drive analysis and optimization of our IP.
• Converting R&D concepts into real implementation solutions.
• Enable our partners to achieve the best possible quality of results.

• Bachelors or Master’s degree equivalent in Electrical Engineering, Computer Engineering or other relevant technical fields.
• 8 to 12 Years years of proven experience in ASIC Implementation, Physical design, STA and Timing closure, Structured clock tree, PDN analysis, DFM and Physical verification
• The ability to demonstrate that you can express new insights and communicate them effectively. Possess a high level of dedicated, initiative and problem-solving skills.
• Experience in crafting and adopting new silicon implementation techniques and methodologies and promote their use with international teams
• Previous experience in and knowledge of the entire IC design flow, from RTL through to GDS2. Proven programming and scripting skills eg. Tcl, Perl, R, Make, sh.

• Knowledge around Arm based CPUs and SoCs!
• Experience with low power design techniques (power gating, voltage/frequency scaling)
• Experience with Verilog RTL design.
• Experience with ATPG tools/and or production testing.

We are proud to have a set of behaviors that reflect our culture and guide our decisions, defining how we work together to defy ordinary and shape outstanding!

• Partner and customer focus
• Teamwork and communication
• Creativity and innovation
• Team and personal development
• Impact and influence
• Deliver on your promises

As part of the methodology team, you will be responsible for developing and leading sophisticated power estimation and optimization methodologies at the netlist (gate-level) stage across SoC and IP designs. You will drive correlation strategies, automation flows, and accuracy improvements to ensure power estimates are tightly aligned with final silicon behavior. This role requires deep technical expertise in power analysis tools, a strong understanding of low-power design techniques, and collaboration with multi-functional teams across the design and verification cycle.

• Define and drive netlist-level power estimation methodologies using industry-leading tools (e.g., Synopsys PrimeTime PX, Cadence Voltus).
• Establish and maintain correlation frameworks between RTL and gate-level power, and between estimated and silicon power.
• Develop automated flows for toggling activity generation, vector-based and vectorless power estimation, and regression reporting.
• Analyze power consumption trends and identify hotspots; provide recommendations for low-power design optimization.
• Collaborate with RTL design, physical design, DFT, and architecture teams to ensure early and accurate power signoff.
• Lead methodology development for corner analysis, dynamic/static power separation, and voltage scaling assessments.
• Support signoff reviews, audits, and compliance to power specifications and constraints.
• Provide mentorship and technical leadership within the team and across global sites.

• 10+ years of proven experience in power estimation, optimization, and methodology development at the gate-level/netlist stage.
• Hands-on expertise with tools such as Synopsys PrimeTime PX, Cadence Voltus, and related signoff flows.
• Strong understanding of digital design principles, low-power architecture techniques, clock gating, and multi-voltage domains.
• Proficient in scripting (Python, Perl, TCL) to develop scalable and automated power analysis flows.
• Demonstrated experience in analyzing switching activity data (SAIF/VCD/FSDB) and correlating to real application workloads.
• Confirmed ability to handle large SoC designs and deliver accurate power metrics under tight schedules.
• Excellent problem-solving skills, attention to detail, and ability to drive technical discussions and decisions.

• Experience with UPF/CPF power intent validation and integration.
• Exposure to thermal and IR-drop analysis in relation to power consumption.
• Familiarity with AI/ML-based power modeling or anomaly detection.
• Previous contributions to methodology deployment in domains such as mobile, automotive, or server-grade SoCs.
• Participation in EDA tool evaluations, benchmarking, and vendor teamwork.
• Publications or presentations in technical forums (e.g., SNUG, DVCon, DAC) related to power estimation or optimization.

We are proud to have a set of behaviors that reflects who we are and guides our decisions, defining how we work together to surpass ordinary and shape outstanding!

• Partner and dedication towards or customers
• Collaborate and communication
• Originality and resourcefulness
• Team and personal development
• Impact and influence
• Deliver on your promises

Responsibilities include

• Lead the productization and system integration work for our Automotive Solution Software team.
• Provide technical expertise and leadership to the team, including leading and line managing a team of engineers.
• Analyse system software and hardware architecture specs, roadmap requirements to create software integration & delivery strategy and project plans.
• You will be actively involved in software design and creation of stacks for Arm’s reference platforms, and lead development practices for best-in-class software efficiency, quality, and predictability.

Good university degree (or equivalent experience), ideally in a numerate subject.

• An ideal candidate will have a broad background in multiple aspects of system software development with a strong focus on technology and shipping products.
• You possess expertise in low-level systems software, OS fundamentals (preferably Linux), a good understanding of computer architecture and microarchitecture concepts, ideally for the Arm architecture.
• You have strong experience of the software lifecycle with track record of having taken complex software from concept to delivery, ideally covering production and maintenance. Additionally, you possess knowledge of CI (Continuous Integration) and automated test systems.
• You have experience and skills for people management, including recruiting, managing talent, team building, and developing team members.
• You have experience of breaking down and estimating complex requirements at different stages of the project lifecycle

• Experience with open source projects such as Linux, Yocto, AOSP, TF-A, TF-M, UEFI EDK II, U-Boot, Xen, Zephyr.
• Exposure to Automotive workloads, AI / ML software stacks, and tooling.
• Experience with Safety and Security Development practices.

• Lead the development and deployment of sophisticated front-end methodologies for ASIC design, including Verification, SoC Integration, LEC, and Implementation processes.
• Drive and deliver customer-centric automation and tool development initiatives in collaboration with IT and software teams.
• Lead all aspects of migration strategies for major EDA tool transitions (e.g., CDC 0in to SpyGlass, RealIntent RDC to VC RDC).
• Collaborate closely with worldwide vendor R&D and AE teams to evaluate and deploy AI and automation solutions for ASIC workflows.
• Orchestrate RTL quality improvement initiatives including CDC SVA-based verification, Lint optimization, and formal verification improvements.
• Own vendor management responsibilities, including SOWs, important metric tracking, license management, tool evaluation, and documentation.
• Represent the company in technical conferences, working groups, and internal award forums.

• 15+ years of experience in VLSI ASIC design, verification, and methodology development.
• Confirmed leadership in setting up and handling high-performance teams and engineering charters.
• Expertise in EDA tools such as SpyGlass, VC RDC, LEC, Design Compiler, VCFSM, and formal verification tools.
• Proficiency in scripting and automation using Python, Perl, TCL.
• Strong understanding of Verilog/SystemVerilog and front-end design verification techniques (CDC, Lint, FV).
• Experience with tool migrations and performance benchmarking.
• Solid background in multi-functional collaboration with software, IT, and program management teams.
• Exceptional communication, collaborator management, and technical program leadership.

• Experience with AI flow optimization and automation in EDA environments.
• Familiarity with automotive and compute SoC programs and compliance processes.
• Awards or accolades demonstrating innovation, execution excellence, and peer recognition.

We are proud to have a set of behaviors that reflects who we are and guides our decisions, defining how we work together to surpass ordinary and shape outstanding!

• Partner and dedication towards or customers
• Collaborate and communication
• Originality and resourcefulness
• Team and personal development
• Impact and influence
• Deliver on your promises

Arm System IP enables designers to build Arm AMBA systems that are high performance, power efficient and reliable. Configurable for many different applications, System IP is the right choice for your system whether it is a high-efficiency IoT endpoint or a high-performance server SoC.

Our group is seeking dedicated verification engineers to deploy and implement designs and products.

• Build and maintain detailed verification plans/strategies for our next generation interconnect designs.
• Work alongside architects and designers to debug and develop new features balancing the needs of multiple partners in our product development cycle.
• Architect and develop sophisticated and efficient SystemVerilog/UVM based test benches.
• Debug functional regression failures, close coverage and drive improvements.

• Bachelors, Masters or PhD in Electrical/Computer Engineering or Computer Science
• 7+ years of experience in verification/RTL design.
• Multiprocessing microarchitecture experience including knowledge of cache coherence and bus protocols (e.g. AMBA5 CHI, AMBA4 ACE or AXI).
• Previous experience in specification, creation, and debug of System Verilog/UVM constrained-random testbenches.
• Software engineering skills including understanding of object-oriented programming, data structures, and algorithms.
• Proficiency with functional coverage verification methods.

• Knowledge of high speed protocols such as PCI Express (PCIe), SATA, USB and Ethernet.
• Excellent knowledge of scripting languages such as Python or Perl.
• Experience in Formal Verification techniques is a plus.