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About the Role
We are working on exciting projects, connecting materials to systems, to drive new innovations that enable a wide range of advanced Logic-Memory devices and technologies, and associated material and processes interactions. You can be part of this cutting-edge modeling and design team, where you will have the opportunity to model and simulate new technologies that answers the continuous demands for scaled devices, denser interconnects that significantly improves the system Power, Performance and Area (PPA).
This primary responsibility of this position will be to focus on DTCO modeling to support the unit process and integration flow development for next generation logic and DRAM nodes. You will play a key role in shaping the future of advanced logic and DRAM technologies by providing DTCO simulation-driven insights that influence materials, process and design decisions.
Key Responsibilities
Development of TCAD process and device models to enable predictive analysis for advanced logic (FinFET, GAA, CFET) and DRAM architectures (6F2, 4F2 VCT and 3D DRAM)
Development and modification of speculative process integration schemes and risk/benefit assessment.
Extraction of compact model representation of TCAD simulated devices.
Layout development/design of standard logic cells and DRAM array
Interconnect modeling and parasitic resistance and capacitance extraction
SPICE modeling and PPA projection for benchmark logic circuits & blocks and DRAM array / periphery
Collaborate with cross-functional teams to define simulation requirements, interpret results, and provide actionable design and process recommendations.
Support technology roadmap development by evaluating new materials, interconnect structures, process flows and design.
Drive design-of-experiment (DOE) studies and sensitivity analyses to understand key drivers of electrical performance and reliability.
Contribute to the development and automation of internal simulation workflows, tools, and best practices to improve modeling efficiency and accuracy.
Document and present simulation methodologies, results, and recommendations to both technical and executive audiences.
Stay current with industry trends, emerging technologies, and academic research in advanced packaging and simulation methodologies.
Required Qualifications
Master’s or Ph.D. in Electrical Engineering, Materials Science, Applied Physics, or a related field.
5–10 years of hands-on industry experience with Synopsys 3D TCAD process, device, parasitic extraction and spice modeling tools towards logic or memory technology development.
Strong fundamental understanding of semiconductor device physics related to logic and DRAM technologies.
Familiarity with logic (FinFET, GAA and CFET) and DRAM process integration flows (FEOL / MOL / BEOL) and 3D device structures.
Experience with logic benchmark circuits and PPA evaluation methodologies.
Experience with DRAM array and periphery operation.
Experience with scripting and automation (e.g., Python, TCL, MATLAB) to streamline simulation workflows.
Excellent analytical, problem-solving, and communication skills.
Proven ability to work independently and collaboratively in a fast-paced, cross-functional environment.
Strong problem-solving abilities in interdisciplinary areas
Ability to present scientific and/or experimental results in a concise and convincing manner
Desire to stay up to date with industry challenges and recent advancements
Passionate and highly motivated to learn new things
Preferred Qualifications
Experience with device and circuit level reliability modeling
Recent experience with writing research papers for conference and journal publications
Experience with standard cell characterization, RTL synthesis, DRC/LVS and place-and-route and timing analysis flows
Experience in calibration tohardware/measurementsand correlations
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What We Offer
$179,500.00 - $246,500.00Santa Clara,CA About the Role
We are looking for an expert, highly experienced Senior FEA Engineer to join our Advanced Packaging Modeling team in Santa Clara, CA. This is a critical role focused on developing thermal-mechanical simulations to support the design, development, and qualification of next-generation semiconductor packaging technologies. You will play a key role in shaping the future of advanced packaging by providing simulation-driven insights that influence architecture, materials, and process decisions.
This position offers the opportunity to work at the forefront of semiconductor innovation, collaborating with engineers and researchers across multiple business units including design, process integration, reliability, and manufacturing.
Key Responsibilities
Develop and validate detailed finite element analysis (FEA) models to simulate thermal and mechanical behavior of advanced semiconductor packages.
Perform simulations to evaluate stress, strain, warpage, delamination, thermal cycling, and reliability risks across a wide range of package architectures (e.g., flip-chip, fan-out, 2.5D/3D IC, chiplet-based designs, TSVs).
Conduct thermal modeling to assess heat dissipation in complex package structures, supporting thermal design optimization and advanced cooling technology development.
Collaborate with cross-functional teams to define simulation requirements, interpret results, and provide actionable design and process recommendations.
Support technology roadmap development by evaluating new materials, interconnect structures, and process flows from a thermo-mechanical reliability perspective.
Drive design-of-experiment (DOE) studies and sensitivity analyses to understand key drivers of package performance and reliability.
Contribute to the development and automation of internal simulation workflows, tools, and best practices to improve modeling efficiency and accuracy.
Document and present simulation methodologies, results, and recommendations to both technical and executive audiences.
Stay current with industry trends, emerging technologies, and academic research in advanced packaging and simulation methodologies.
Required Qualifications
M.S. or Ph.D. in Mechanical Engineering, Materials Science, Applied Physics, or a related field.
5–10 years of hands-on industry experiencein thermal-mechanicalFEA modeling, in the semiconductor or electronics packaging domain.
Thorough understanding of advanced packaging technologies, including flip-chip, fan-out wafer-level packaging (FOWLP), 2.5D/3D integration, chiplet architectures, and through-silicon vias (TSVs).
Proficient with commercial FEA tools such as ANSYS, Abaqus, COMSOL, or equivalent.
Strong knowledge of materials behavior, including polymers, metals, ceramics, and their interactions under thermal and mechanical loads.
Familiaritywith semiconductorpackaging processes, including die attach, underfill, molding, bumping, and reflow.
Excellent analytical, problem-solving, and communication skills.
Proven ability to work independently and collaboratively in a fast-paced, cross-functional environment.
Preferred Qualifications
Experiencewith multi-physicssimulations, including coupledelectro-thermal-mechanicalanalysis.
Familiarity with JEDEC reliability standards and qualification tests (e.g., TCoB, HTS, uHAST, drop test).
Experience with scripting andautomation (e.g.,Python, TCL, MATLAB) to streamline simulation workflows.
Exposure to package design tools such as Cadence, Mentor Graphics, or equivalent.

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Key Responsibility:
Skills, Experience, and Education:

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What We Offer
$138,000.00 - $190,000.00Santa Clara,CAApplied Materials’ is looking to recruit an outstanding engineer to support its computational modeling group. In this role, you will use state-of-the-art simulation tools to simulate the complex multi-physics environment in Applied Materials’ products and work closely with engineers across multiple business units to develop new solutions to difficult problems. You will work closely with design and process engineers to enhance existing products as well as play a key role in the development of next-generation chambers and processes.
Required qualifications:
-PhD inComputer/Mechanical/Aerospace/ChemicalEngineering or related field
-Hands-on experience applying machine learning, statistical analysis, anddesign-of-experimentstechniques to simulation and modeling workflows
-Comfortable working with large-scale datasets and extracting actionable insights
-Proficient in one or more programming languages (e.g., C/C++,MATLAB/Python/etc.)
-Strong communication skills, both written and verbal
Experience with one or more of the following:
- commercial and/or academic plasma simulation tools (e.g., HPEM, Ace+, VizGlow, Comsol, VSim)
- commercial and/or academic multi-physics simulation tools (e.g. Ace+, Ansys, Comsol)
- electromagnetic and magnetostatic simulation tools (e.g., Ansys HFSS, Ansys Maxwell)
- deep understanding of chemical kinetics and fluid dynamics for industrial applications
- hands-on experience with solver and algorithm development
- hands-on experience with UI development

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Key Responsibilities
Design, collect data, analyze and compile reports on a wide range of complex process engineering experiments for multiple products, within safety guidelines
Utilize techniques to characterize hardware, define methods and apply new technologies to characterize hardware, and/or perform hardware characterization on a wide range of complex systems for multiple products, within safety guidelines
Generate internal and external documentation for products, presentations, technical reports and generate process engineering specifications
Develop, plan and execute process engineering projects, within safety guidelines
Train engineers in measurement techniques of film properties and guide them in the interpretation of the data, new methodologies, trouble shooting techniques and resolve a wide range of complex process engineering issues/problems for multiple products
Design and implement new technology, products and analytical instrumentation
Identify, select and work with vendors and suppliers with limited to no supervision
Functional Knowledge
Business Expertise
Leadership
Problem Solving
Impact
Interpersonal Skills

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Key Responsibilities
Functional Knowledge
Business Expertise
Leadership
Problem Solving
Impact
Interpersonal Skills

Share
What We Offer
$64,000.00 - $88,000.00
General Profile:Requires knowledge and experience in own discipline; still acquiring higher-level knowledge and skills. Builds knowledge of the company, processes and customers. Solves a range of complex problems. Analyzes possible solutions using standard procedures. Receives a moderate level of guidance and direction.
Problem Solving (2 - Working Experience); Planning: Tactical and Strategic (1 - Basic Understanding); Reliability Engineering (0 - No Experience); Collaboration (2 - Working Experience); Data Analytics (1 - Basic Understanding); Quality Methodologies (0 - No Experience); CI Product Characterization (2 - Working Experience); Knowledge Transfer and Management (1 - Basic Understanding); Leading Change (1 - Basic Understanding); CI Methodologies (2 - Working Experience); Listening & Communication (1 - Basic Understanding); Producing Results (1 - Basic Understanding); Project Management (1 - Basic Understanding); Accuracy & Attention to Detail (2 - Working Experience); Influencing (2 - Working Experience); Decision Making and Critical Thinking (1 - Basic Understanding)
Key Responsibilities
Lead optimization of the Value Stream by elimination of waste and making flow improvements across or within manufacturing, supply chain, logistics, and/or service product operations.
Lead and facilitate Lean Six Sigma process improvement methods and tools to eliminate waste and drive continuous improvement. Deliver improvements to Operation’s KPI’s.
Lead Kaizen Events, 8D and Green Belt level projects within and across operations to optimize performance.
Functional Knowledge
Business Expertise
Leadership
Problem Solving
Impact
Interpersonal Skills
Education:Technical Diploma
4 - 7 Years
Full timeAssignee / Regular
Share
About the Role
We are working on exciting projects, connecting materials to systems, to drive new innovations that enable a wide range of advanced Logic-Memory devices and technologies, and associated material and processes interactions. You can be part of this cutting-edge modeling and design team, where you will have the opportunity to model and simulate new technologies that answers the continuous demands for scaled devices, denser interconnects that significantly improves the system Power, Performance and Area (PPA).
This primary responsibility of this position will be to focus on DTCO modeling to support the unit process and integration flow development for next generation logic and DRAM nodes. You will play a key role in shaping the future of advanced logic and DRAM technologies by providing DTCO simulation-driven insights that influence materials, process and design decisions.
Key Responsibilities
Development of TCAD process and device models to enable predictive analysis for advanced logic (FinFET, GAA, CFET) and DRAM architectures (6F2, 4F2 VCT and 3D DRAM)
Development and modification of speculative process integration schemes and risk/benefit assessment.
Extraction of compact model representation of TCAD simulated devices.
Layout development/design of standard logic cells and DRAM array
Interconnect modeling and parasitic resistance and capacitance extraction
SPICE modeling and PPA projection for benchmark logic circuits & blocks and DRAM array / periphery
Collaborate with cross-functional teams to define simulation requirements, interpret results, and provide actionable design and process recommendations.
Support technology roadmap development by evaluating new materials, interconnect structures, process flows and design.
Drive design-of-experiment (DOE) studies and sensitivity analyses to understand key drivers of electrical performance and reliability.
Contribute to the development and automation of internal simulation workflows, tools, and best practices to improve modeling efficiency and accuracy.
Document and present simulation methodologies, results, and recommendations to both technical and executive audiences.
Stay current with industry trends, emerging technologies, and academic research in advanced packaging and simulation methodologies.
Required Qualifications
Master’s or Ph.D. in Electrical Engineering, Materials Science, Applied Physics, or a related field.
5–10 years of hands-on industry experience with Synopsys 3D TCAD process, device, parasitic extraction and spice modeling tools towards logic or memory technology development.
Strong fundamental understanding of semiconductor device physics related to logic and DRAM technologies.
Familiarity with logic (FinFET, GAA and CFET) and DRAM process integration flows (FEOL / MOL / BEOL) and 3D device structures.
Experience with logic benchmark circuits and PPA evaluation methodologies.
Experience with DRAM array and periphery operation.
Experience with scripting and automation (e.g., Python, TCL, MATLAB) to streamline simulation workflows.
Excellent analytical, problem-solving, and communication skills.
Proven ability to work independently and collaboratively in a fast-paced, cross-functional environment.
Strong problem-solving abilities in interdisciplinary areas
Ability to present scientific and/or experimental results in a concise and convincing manner
Desire to stay up to date with industry challenges and recent advancements
Passionate and highly motivated to learn new things
Preferred Qualifications
Experience with device and circuit level reliability modeling
Recent experience with writing research papers for conference and journal publications
Experience with standard cell characterization, RTL synthesis, DRC/LVS and place-and-route and timing analysis flows
Experience in calibration tohardware/measurementsand correlations
These jobs might be a good fit