Design Integration Engineer jobs at Apple in United States, San Diego
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United States
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San Diego
552 jobs found
31.05.2024
A
Apple Design Integration Engineer United States, California, San Diego
Knowledge of the ASIC design flow, synthesis, static timing analysis, scripting, and netlist generation. Understanding of UPF and low-power design & implementation techniques. Hands-on experience in timing/SDC constraints generation, analysis,...
Knowledge of the ASIC design flow, synthesis, static timing analysis, scripting, and netlist generation. Understanding of UPF and low-power design & implementation techniques. Hands-on experience in timing/SDC constraints generation, analysis,...
Drive new memory system architectures from DRAM up. Explore architecture and feature trade-offs in system performance, area, and power consumption. Develop memory hierarchies for high performance parallel computer architectures. (system-on-a-chip...
This is a comprehensive technical contributor role that requires validated experience in system design, integration, bringing up and productization of wireless communication systems. Prefers experience bringing up a wireless chip...
BS and 3+ years of relevant industry experience. This position requires thorough knowledge of the ASIC design flow, FE, Low power design and design verification, scripting. Knowledge of ASIC/SoC design...
BS and 3+ years of relevant industry experience. Experience with physical design, integration, and verification (PDV) experience on large processor and/or SoC designs. Knowledge of industrial standards and practices in...
Strong background in board-level analog and mixed-signal circuits and/or embedded systems; hands-on experience in module-level design. Proficiency in simulation tools (such as COMSOL/SPICE), scripting languages (such as Python/MATLAB), and statistical...
Knowledge of the ASIC design flow, synthesis, static timing analysis, scripting, and netlist generation. Understanding of UPF and low-power design & implementation techniques. Hands-on experience in timing/SDC constraints generation, analysis,...
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