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Soc Design/integration & Synthesis Engineer jobs at Apple in United States, Cupertino
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Cupertino
1,532 jobs found
11.07.2024
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Apple SoC Design/Integration & Synthesis Engineer United States, California, Cupertino
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BS and a minimum of 10 years relevant industry experience. Expertise in digital design integration, synthesis, UPF, timing analysis, and closure. Synthesis/Integration of RTL background and basic understanding of UPF....
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10.07.2024
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Apple SoC Design/Integration & Synthesis Engineer United States, California, Cupertino
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BS degree + 3 years of industry experience is required. Expertise in digital design integration, synthesis, UPF, timing analysis, and closure. Worked closely on improving low-power synthesis methodologies. Hands-on experience...
14.06.2024
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Apple SoC Design Integration Engineer United States, California, Cupertino
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Hands on experience in all aspects of the chip development process with proficiency in front end tools and methodologies. Experience writing specifications and converting them to design. Experience with multiple...
31.05.2024
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Apple SoC Integration Engineer United States, California, Cupertino
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Deep experience in RTL Logic Design of multi-million gate ASICs. Hands on experience for all aspects of the chip development process with proficiency in front end tools and methodologies related...
05.06.2024
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Apple ASIC Design Integration Engineer United States, California, Cupertino
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Substantial knowledge of LPDDR memory and memory controller. General knowledge of DRAM interface calibration mechanism is a plus. Hands on experience in micro architecture definition, RTL coding, low power design...
05.06.2024
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Apple ASIC Design Integration Engineer United States, California, Cupertino
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RTL Logic Design experience of multi-million gate ASICs. Hands on experience in all aspects of the chip development process with proficiency in front-end tools and methodologies. Experience writing specifications and...
21.09.2024
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Apple Physical Synthesis CAD Engineer United States, California, Cupertino
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Experience with TCL, Python or Perl scripting languages. Knowledge of Logic design fundamentals. Experience with Synthesizable System Verilog RTL. Minimum requirement of BS + 0 years of relevant industry experience....
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Description:Full job details
BS and a minimum of 10 years relevant industry experience. Expertise in digital design integration, synthesis, UPF, timing analysis, and closure. Synthesis/Integration of RTL background and basic understanding of UPF....
These jobs might be a good fit
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