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Cpu Performance Workload Analysis Architect - Platform Architecture jobs at Apple in United States, Beaverton
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Beaverton
35 jobs found
01.08.2025
A
Apple CPU Implementation Engineer United States, Oregon, Beaverton
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Description:
As a CPU Implementation Engineer, you will own or participate in the following:• Work extensively with Micro-architects to define memory subsystem, perform feasibility, make area, frequency, performance, power trade-offs and design and balance the pipeline stages.• Drive RTL-to-GDS flow through synthesis and place-and-route targeting ambitious targets for power, performance, and area.• Design delivery. Work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability, and power.
- Minimum BS and 10+ years of relevant industry experience
- Experience in VLSI or digital circuit design
- Experience with scripting in Perl or TCL
- Familiarity with high performance microprocessor architecture
- Knowledge of logic design principles along with timing and power implications
- Understanding of low power microarchitecture and implementation techniques
- Design experience in deep sub-micron technologies and device physics
- Experience using synthesis & place-route tools
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27.07.2025
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Apple CPU Implementation Feasibility Engineer United States, Oregon, Beaverton
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In this role, core responsibilities include, but are not limited to the following: Designing and simulating wireless communication systems for 5G and 6G technologies, including channel coding, advanced MIMO systems, protocols for energy saving, AI/ML for air interface enhancements, sensing techniques, control and data channel optimization for cellular systems. Attending global standards meetings, including 3GPP, to promote Apple product preferences. Collaborate with product teams and come up with novel architecture, protocols, and algorithms to meet the requirements of emerging applications in a challenging radio environment.
- Working knowledge of wireless communication systems (e.g., OFDM/MIMO, etc.).
- Proven experience in the algorithm development and implementation design of communication systems or signal processing algorithms, and ability to develop and implement performance tuning strategies and optimizations.
- Experience with Matlab or Python and/or C/C++ for algorithm development, modeling, and simulation.
- Excellent communication skills to collaborate with cross-functional teams.
- Motivated to collaborate and contribute as a team, and able to deliver ambitious tasks in a timely manner.
- BS and 3+ years of relevant experience is required.
- Ph.D. with a focus on communication systems, signal processing or AI/ML for wireless communication
- Knowledge in existing wireless communication protocols, such as 5G/LTE/WCDMA/GSM, 802.11a/b/g/n/ac/ax/be, 802.11ad/ay or Bluetooth/BLE.
- Strong understanding of communication theory and relevant algorithm design experience on, including but not limited to, timing recovery, automatic gain control, modulation, channel estimation, equalization, MIMO signal estimation and detection, channel coding and error correction, and beam forming algorithms
- Experience in designing systems that operate efficiently in high-load and noisy environments.
- Experience on low-power algorithm design for power critical applications.
- Experience with multi-radio coexistence management.
- Deep understanding of components/modules within wireless communication systems, and the possible impairments from those components, and the corresponding calibration and impairment reduction methods/algorithms, digital pre-distortion, PAPR reduction algorithms, Tx power control, etc.
- Experience in modem architecture, microprocessor architecture, hardware and software control.
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13.07.2025
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Apple Game Engineer Platform Architecture United States, Oregon, Beaverton
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Description:
We value your ability to lead and implement safety, security, and shrink mitigation strategies, which safeguard the Company’s assets and provide clear guidance to team members. Through store visits, you'll identify preventative shortage reduction measures, inspect and follow company safety policies, provide direction and training to ensure opportunities are identified and corrected. You'll work closely with all levels of management to ensure that all aspects of Retail Security are consistent and in compliance with company standards. Providing support, guidance, and training to all stores within defined market/area regarding Retail Security, you will be responsible for a variety of tasks including (but not limited to) managing security budgets, assisting with internal and external investigations, ensuring consistent practices among stores, conducting safety audits, and developing market specific shortage action plans in high-risk stores. Responsible for the safety of our employees, investigations, operational standards, training, and budgets in assigned market(s) and working with stores to identify inventory shortage opportunities and recommend resolutions. You will be responsible for managing security vendors in assigned market(s).
- 5-7 years of retail loss prevention/security leadership experience operating in a multi store environment
- Ability to travel to stores within assigned area, manuever around sales floors, stock rooms and offices
- Wicklander & Zulawski or Reid investigative interviewing certification preferred
- Certified Forensic Interviewer preferred
- Experience in assessing store and market needs to ensure security programs, safety elements, and investigative resources are being properly deployed
- Experience developing recommendations and solutions in crisis situations such as work place violence and active threats
- Excellent communication, written and verbal
- Flexibility to work all shifts (nights, weekends, holidays) and willingness to support the team as needed
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
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28.06.2025
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Apple CPU Performance Engineer United States, Oregon, Beaverton
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Description:
- Minimum BS and 10+ years of relevant industry experience
- Experience in CPU performance architecture, performance modeling, micro-architecture design, performance analysis
- Experience with C and C++ and at least one of the following scripting languages: Perl or Python
- Bachelor of Science or Engineering in Electrical Engineering, Computer Engineering, or Computer Science
- Knowledge and experience with common performance benchmarks and workloads
- Knowledge of OS internals and compiler technology is a plus
- Ability to problem solve and prove your own ideas
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08.06.2025
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Apple CPU Implementation Engineer United States, Oregon, Beaverton
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Description:
As a CPU Implementation Engineer, you will drive or participate in the following:• Work with micro-architects to help define the micro-architecture and assist with design feasibility and power, performance, and area (PPA) trade-offs• Drive RTL-to-GDS design convergence through microarchitecture and logic (RTL) optimizations using synthesis and place-and-route tools targeting ambitious goals for PPA• Responsible for block-level design delivery along with closure of backend flows, electrical requirements, and improving silicon yield• Work closely with internal CAD and PD methodology teams on industry standard synthesis/PNR tool features and optimizations and their adoption in CPU design• Work with x-functional top-level teams on the aspects of CPU floorplan, timing, power, reliability, and testability• Work closely with custom IP teams to define and co-optimize memory macros, library standard cells to improve design PPA
- Minimum BS and 10+ years of relevant industry experience
- Experience in logic design and digital circuits
- Experience with low power and high frequency design techniques
- Experience in TCL or Perl
- Familiarity with high performance CPU microprocessor architecture and memory sub-system
- Knowledge in deep sub-micon technology along with its implications to timing, power, and area
- Must have proficiency in using industry standard logic Synthesis, PnR, STA and Power analysis tools along with floor-planning, physical design partitioning, and timing budgeting, to converge complex designs
- Excellent communication and interpersonal skills
- Ability to work independently and/or lead a physical design partition in collaboration with x-functional teams
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08.06.2025
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Apple CPU Cache Microarchitect/RTL Engineer United States, Oregon, Beaverton
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Description:
As a CPU RTL Architect, you will own or participate in the following: • Micro-architecture development and specification - from early high-level architectural exploration, through micro-architectural research and arriving at a detailed specification. • RTL ownership - development, assessment and refinement of RTL design to target power, performance, area and timing goals. • Verification - support the verification team in test bench development, formal methods, and simulation/emulation for formal verification • Performance exploration and correlation - explore high-performance strategies and work with the performance verification team to verify that the RTL design meets targeted performance. • Design delivery - work with multi-functional engineering team to implement and verify physical design on the aspects of timing, area, reliability, testability and power.
- Minimum BS and 10+ years of relevant industry experience
- Experience with microprocessor cache design or coherent system cache design
- Experience with Verilog and/or VHDL
- Knowledge of microprocessor architecture
- Experience with simulators and waveform debugging tools
- Expertise in one or more of the following areas: Coherence protocols and interconnects, high performance (low latency, high bandwidth) design techniques, or memory subsystem queuing, scheduling; starvation and deadlock avoidance
- SRAM design basics
- Multiple clock/power domains and power management strategies
- Prefetchers, replacement policies
- Debug capabilities
- DFT strategies
- Error detection and correction
- Understanding of low power microarchitecture techniques
- Understanding of high-performance techniques and trade-offs in a CPU microarchitecture
- Experience in C or C++ programming
- Experience using an interpretive language such as Perl or Python
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07.06.2025
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Apple CPU Debug Power Management Microarchitect/RTL Engineer United States, Oregon, Beaverton
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Description:
As a CPU Debug and Power Management Microarchitect/RTL Engineer, you will own or contribute to the following:• RTL ownership of CPU debug, trace, power management, clock management, and timer logic - development, assessment, and refinement of RTL design to target power, performance, area and timing goals• Micro-architecture development and specification - Work with a cross-functional team of silicon and software experts to explore and define architectural features, develop micro-architectural details, and arrive at a detailed specification• Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional verification• Performance exploration and correlation - explore high performance strategies and work with the performance verification team to verify that the RTL design meets targeted performance• Design delivery - Aid in debug of issues at SoC level related to CPU power management, clock control, and debug features. Work with multi-functional engineering team to implement and verify physical design on the aspects of timing, area, reliability, testability and power
- Minimum BS and 10+ years of relevant industry experience
- Experience with Verilog or VHDL
- Experience with simulators and waveform debugging tools
- Experience with logic design with timing and power implications
- Knowledge and understanding of microprocessor architecture
- Expertise in one or more of the following areas: multiple clock/power domains and power management strategies, hardware debug and trace capabilities, DFT strategies, interrupt controllers, memory subsystem queuing, scheduling - starvation and deadlock avoidance, fabric communication protocols and interconnects
- SRAM design basics
- Understanding of low power microarchitecture techniques
- Understanding of high-performance design techniques and trade-offs
- Experience in C or C++ programming
- Experience using an interpretive language such as Python or Perl
Expand
Share
Description:
As a CPU Implementation Engineer, you will own or participate in the following:• Work extensively with Micro-architects to define memory subsystem, perform feasibility, make area, frequency, performance, power trade-offs and design and balance the pipeline stages.• Drive RTL-to-GDS flow through synthesis and place-and-route targeting ambitious targets for power, performance, and area.• Design delivery. Work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability, and power.
- Minimum BS and 10+ years of relevant industry experience
- Experience in VLSI or digital circuit design
- Experience with scripting in Perl or TCL
- Familiarity with high performance microprocessor architecture
- Knowledge of logic design principles along with timing and power implications
- Understanding of low power microarchitecture and implementation techniques
- Design experience in deep sub-micron technologies and device physics
- Experience using synthesis & place-route tools
Expand
These jobs might be a good fit
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