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Job Area:
Engineering Group, Engineering Group > Hardware Engineering
Minimum of 7+ years experience in the area of ASIC/DFT
-In depth knowledge of DFT concepts
-In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis
-Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations
-Expertise in scripting languages such as perl, shell, etc.
-Experience in simulating test vectors
-Knowledge of equivalence check, DFT DRC rules both in RTL lint tool (like spyglass) and ATPG tool like (TK, TetraMax)
-Working experience in Synopsis TetraMax/DFTMax and Cadence Encounter Test is a plus
-Ability to learn and adapt to new tools and methodologies.
-Ability to do multi-tasking & work on several high priority designs in parallel.
-Excellent problem solving skills
-Excellent communication and team work skills and good English is required
Minimum Qualifications:
• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.
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