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Cad Engineer - Timing Gate-level Flows & Methodologies jobs at Apple in United States, Texas, Austin

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274 jobs found
Today
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Apple CAD ML Timing Optimization Engineer United States, Texas, Austin

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Description:
Practical knowledge and experience in applying ML and/or GPU accelerated approaches to solving challenging optimization tasks. Proven software engineering background and experience with C++, Python, and a variety of deep...
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16.05.2024
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Apple Timing Design Engineer United States, Texas, Austin

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Description:
Prefers extensive and relevant experience in Physical Design on high PHY and/or SOC designs. Deep knowledge of industry standards and practices in Timing closures, Physical Design, including Physically aware synthesis,...
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Yesterday
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Apple CAD Engineer- Signoff PNR United States, Texas, Austin

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Description:
We are looking for:. Knowledge of PNR design flows. Experience with PNR tools such as ICC, EDI, Primetime, Tempus. Good understanding of STA and Noise analysis flows. Experience in timing...
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Today
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Apple Physical Design Methodology CAD Engineer United States, Texas, Austin

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Description:
Experience in CAD flow or PD methodology development. Proficiency with Tcl, Python or Perl scripting languages. Hands on knowledge of industry standard PNR tools. Understanding and experience in analysis aspects...
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Today
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Apple CPU Silicon Timing Correlation Engineer United States, Texas, Austin

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Description:
Minimum BS and 10+ years of relevant industry experience. Good all round hardware and data analysis skills. Good understanding of VLSI design practice and static timing analysis. Data analysis skills...
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15.05.2024
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Apple CAD Engineer- Signoff PNR United States, Texas, Austin

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Description:
We are looking for:. Demonstrated experience in PNR design flows. Experience with PNR tools such as ICC, EDI, Primetime, Tempus. Understanding of tradeoffs to meet PPA (power, performance, area) targets....
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15.05.2024
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Apple CAD STA Technologist United States, Texas, Austin

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Description:
STA timing closure experience of gate level and transistor level designs in advanced CMOS process. Thorough understanding of STA and methodologies for timing closure, good understanding of noise, cross-talk, and...
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Find your dream job in the high tech industry with Expoint. With our platform you can easily search for Cad Engineer - Timing Gate-level Flows & Methodologies opportunities at Apple in United States, Texas, Austin. Whether you're seeking a new challenge or looking to work with a specific organization in a specific role, Expoint makes it easy to find your perfect job match. Connect with top companies in your desired area and advance your career in the high tech field. Sign up today and take the next step in your career journey with Expoint.