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Apple Design Verification Engineer Sweden 174773049
28.03.2024
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Key Qualifications
- Some working knowledge of SystemVerilog test-bench language and UVM
- Experience developing scalable and portable test-benches
- Experience with verification methodologies and tools such as simulators, waveform viewers, build and run automation, coverage collection, gate level simulations
- Experience with different DDR protocols including Low power version
- Should have been in technical lead position
- Experience with IP verification methodology for IPs such as PHYs, PLLs etc.
- Working knowledge of one of the scripting languages: Python, Perl, TCL
Description
In this role, you will be responsible for ensuring a bug-free first silicon for part of the SoC / IP and are expected to: Lead and develop detailed test and coverage plans based on the micro-architecture. Drive verification methodology suitable for the IP, ensuring a scalable and portable environment. Develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. Develop verification plans for all features under your care. Execute verification plans, including design bring-up, Design Verification environment bring-up, regression enabling for all features under your care, de-bug of the test failures. Develop block, IP and SoC level test-benches Track and report Design Verification progress using a variety of metrics, including bugs and coverage. Develop IP simulation environment and work closely with analog team to ensure overall bug-free IP design.
Education & Experience
BS degree in technical discipline with minimum 10 years of relevant experience.
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