Principal Applied Scientist jobs
Intel Principal Engineer - Silicon Packaging Architect United States, Texas
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Key Responsibilities:
- Lead the co-design of silicon and package, focusing on DDR PHY and mixed signal IP integration for server SOCs.
- Design bump maps, floor plans, and manage area constraints for PHYs, collaborating closely with packaging technical experts.
- Conduct hands-onpackage extractionsand simulations(signal integrity, power integrity)
- Finalize bump-out, floor plan, and area decisions at the end of tech readiness phases.
- Interface with packaging teams on advanced technologies (e.g., C4 bumps, micro bumps, EMIB, hybrid bonding as needed).
- Focus on design, development, and architecture, not process or materials engineering.
Required Experience:
- Experience in both silicon design (preferably mixed signal/analog) and packaging co-design.
- Background in DDR, SOC, or similar high-speed interface development.
- Hands-on expertise with bump mapping, floor planning, and packaging constraints.
- Proven ability to collaborate across silicon and packaging teams, including risk assessment and simulation.
- Familiarity with advanced packaging technologies (hybrid bonding, EMIB, etc.) is a plus but not required.
- Individual contributor or principal engineer level preferred; management experience is not required.
- Experience at leading companies in advanced packaging and PHY design (e.g., Apple, Broadcom, Qualcomm, Micron, AMD, Nvidia).
- Bachelors in electrical engineering, chemical engineering, mechanical engineering, material science or similar field (Master’s or Ph.D. preferred).
- 10+ years in silicon and packaging co-design
Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.
Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
Annual Salary Range for jobs which could be performed in the US:These jobs might be a good fit
Nvidia Senior Quantum Error Correction Research Scientist Applied United States, Texas
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- US, WA, Redmond
- US, CA, Santa Clara
- time type
- Full time
- posted on
- Posted 2 Days Ago
- job requisition id
What you'll be doing:
Path-find technical innovations in Quantum Error Correction and Fault Tolerance, working with multi-functional teams in Product, Engineering, and Applied Research
Develop novel approaches to quantum error correction codes and their logical operations, including methods for implementation and logical operation synthesis
Research and co-design improved methods to achieve fault tolerance, such as techniques for logical operations, concatenation, synthesis, distillation, cultivation, or others
Collaborate with internal teams and external partners on developing technology components to enable a fault-tolerant software stack integrated with quantum hardware
Adopt a culture of collaboration, rapid innovation, technical depth, and creative problem solving
What we need to see:
Degree in Physics, Computer Science, Chemistry, Applied Mathematics, or related engineering field or equivalent experience (Ph.D. preferred)
Extensive background in Quantum Information Science with 8+ overall years of experience in the Quantum Computing industry
A demonstrated ability to deliver high impact value in quantum error correction and fault tolerance
Ways to stand out from the crowd:
Hands-on experience in scientific computing, high-performance computing, applied machine learning, or deep learning
Experience with co-design of quantum error correction with quantum hardware or quantum applications
Experience with CUDA and NVIDIA GPUs
Passion to drive technology innovations into NVIDIA software and hardware products to support Quantum Computing
You will also be eligible for equity and .
Ebay Lead CV Applied Researcher United States, California, San Jose
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As an Sr. Applied Research technical lead at eBay, you will be at the center of how multi-modal intelligence is applied across products. You will not just support AI development, you will lead a team of applied researchers and machine learning engineers to help define how AI driven solutions operate, scale, and deliver value. Your work will directly influence model quality, operational efficiency, and the ways AI enhances user experience across eBay.
Metrics and Reporting:
Define key performance metrics for AI models. Maintain operational excellence standards for data pipelines and models in production
Tools and Technical Fluency
Ph.D. in AI or equivalent research experience. Proficiency in Python and PyTorch for data processing, model training and inference. Expertise in Vision-Language Models and image/video retrieval. Deep understanding of key computer vision techniques for classification, image/video retrieval, 3D modeling, and Image/Video generation. Bonus: experience with frameworks for large-scale multi-GPU training (e.g. PyTorch Lightening, Nemo etc.) and for large scale inference (TensorRT, vLLM )
Two years plus of experience as a tech lead or a manager of science/engineering teams. Comfortable coaching, and enabling team members to deliver high-quality work through clear direction, support, and collaboration.
Quality and Attention to Detail
Detail oriented in how you work with data, models, documentation, and process. Ability to catch inconsistencies early, ensuring standards are consistently met across workflows and deliverables.
The base pay range for this position is expected in the range below:
$210,400 - $280,900Nvidia Senior Research Scientist Generative AI United States, California
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- US, CA, Santa Clara
- time type
- Full time
- posted on
- Posted 2 Days Ago
- job requisition id
NVIDIA is searching for a world-class researcher in generative AI to join our research team. You will be conducting original research for generative AI applications, including image generation, video generation, 3D generation, and audio generation. You will be working with a team of world-class researchers eager to make great impacts with generative AI models. You will be building research prototypes and scaling them with large datasets and compute. After building prototypes that demonstrate the promise of your research, you will work with product teams to help them integrate your ideas into products.
What you'll be doing:
Conduct original research in the space of generative AI
Implement and train large-scale generative AI models for various content creation applications
Collaborate with other research team members, a diverse set of internal product teams, and external researchers
Have a broader impact through the transfer of the technology you've developed to relevant product groups
What we need to see:
Ph.D. in Computer Science/Engineering, Electrical Engineering, or a related field (or equivalent experience).
5+ years of relevant research experience.
Excellent collaboration and interpersonal skills
Excellent python/C++ programming skills
Great knowledge of common deep-learning frameworks
Experience in processing or curating large-scale datasets
Excellent knowledge of theory and practice of deep learning, computer vision, natural language processing, or computer graphics
Track record of research excellence or significant product development
You will also be eligible for equity and .
Nvidia Senior Quantum Error Correction Research Scientist Applied United States, Texas
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- US, WA, Redmond
- US, CA, Santa Clara
- time type
- Full time
- posted on
- Posted 2 Days Ago
- job requisition id
What you'll be doing:
Path-find technical innovations in Quantum Error Correction and Fault Tolerance, working with multi-functional teams in Product, Engineering, and Applied Research
Develop novel approaches to decoding quantum error correction codes and their logical operations, including researching advanced implementations in hardware
Research and co-design improved methods to achieve more scaled decoders
Collaborate with internal teams and external partners on developing technology components to enable a fault-tolerant software stack integrated with quantum hardware
Adopt a culture of collaboration, rapid innovation, technical depth, and creative problem solving
What we need to see:
Masters degree in Physics, Computer Science, Chemistry, Applied Mathematics, or related engineering field or equivalent experience (Ph.D. preferred)
Extensive background in Quantum Information Science with 6+ overall years of experience in the Quantum Computing industry
A demonstrated ability to deliver high impact value in quantum error correction and decoding
Ways to stand out from the crowd:
Hands-on experience in scientific computing, high-performance computing, applied machine learning, or deep learning
Experience with co-design of quantum error correction with quantum hardware or quantum applications
Experience with CUDA and NVIDIA GPUs
Passion to drive technology innovations into NVIDIA software and hardware products to support Quantum Computing
You will also be eligible for equity and .
Nvidia Principal Quantum Error Correction Research Scientist Applie... United States, Texas
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- US, WA, Redmond
- US, CA, Santa Clara
- time type
- Full time
- posted on
- Posted 2 Days Ago
- job requisition id
What you'll be doing:
Path-find technical innovations in Quantum Error Correction and Fault Tolerance, working with multi-functional teams in Product, Engineering, and Applied Research
Develop novel approaches to quantum error correction codes and their logical operations, including methods for implementation and logical operation synthesis
Research and co-design improved methods to achieve fault tolerance, such as techniques for logical operations, concatenation, synthesis, distillation, cultivation, or others
Collaborate with internal teams and external partners on developing technology components to enable a fault-tolerant software stack integrated with quantum hardware
Adopt a culture of collaboration, rapid innovation, technical depth, and creative problem solving
What we need to see:
Masters degree in Physics, Computer Science, Chemistry, Applied Mathematics, or related engineering field or equivalent experience (Ph.D. preferred)
Extensive background in Quantum Information Science with 12+ overall years of experience in the Quantum Computing industry
A demonstrated ability to deliver high impact value in quantum error correction and fault tolerance
Ways to stand out from the crowd:
Hands-on experience in scientific computing, high-performance computing, applied machine learning, or deep learning
Experience with co-design of quantum error correction with quantum hardware or quantum applications
Experience with CUDA and NVIDIA GPUs
Passion to drive technology innovations into NVIDIA software and hardware products to support Quantum Computing
You will also be eligible for equity and .
Unity Principal Workday Architect United States, Oregon
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What you'll be doing
- Lead the design of complex Workday integrations with other enterprise systems, ensuring data integrity and seamless information flow.
- Translate complex business requirements into detailed functional and technical design specifications for Workday configurations and integrations.
- Identify opportunities for process improvement and optimization within Workday to enhance efficiency and user experience.
- Troubleshoot complex Workday issues and provide expert-level support.
- Partner closely with Finance, HR, IT, and other business stakeholders to understand their needs and translate them into Workday solutions
- Progressive experience in ERP implementation, configuration, and support.
- Extensive experience as a Workday Architect or Lead Consultant with a strong focus on large-scale enterprise deployments.
- Deep expertise in Workday Financial Management: Extensive hands-on experience with at least 5+ modules (e.g., GL, AP, AR, FA, Expenses, Projects, Grants, Planning, Accounting, Procurement).
- Extensive experience with Workday Human Capital Management (HCM): Strong understanding of Core HCM, Benefits, Payroll, Absence, Talent Management, Compensation, and Recruiting.
- Demonstrated experience in designing, building, and maintaining Adaptive Planning models, reports, and dashboards.
- Demonstrated experience with Workday integrations (EIB, Core Connectors, Cloud Connect for Third-Party Payroll, Workday Studio).
- Experience with Workday reporting and analytics (e.g., Custom Reports, Dashboards, Discovery Boards).
- Experience in Financial accounting - other ERPs (SAP, Oracle, Peoplesoft, Dynamics 365)
- In-depth understanding of Workday's security model and its application across various modules.
- Proactive, self-motivated, and results-oriented.
- Ability to manage multiple priorities and projects simultaneously.
- Workday certifications in Financials, HCM, and/or Adaptive Planning
- Relocation support is not available for this position.
- Work visa/immigration sponsorship is not available for this position
This position requires the incumbent to have a sufficient knowledge of English to have professional verbal and written exchanges in this language since the performance of the duties related to this position requires frequent and regular communication with colleagues and partners located worldwide and whose common language is English.
Gross pay salary$156,000—$234,000 USDShare
Key Responsibilities:
- Lead the co-design of silicon and package, focusing on DDR PHY and mixed signal IP integration for server SOCs.
- Design bump maps, floor plans, and manage area constraints for PHYs, collaborating closely with packaging technical experts.
- Conduct hands-onpackage extractionsand simulations(signal integrity, power integrity)
- Finalize bump-out, floor plan, and area decisions at the end of tech readiness phases.
- Interface with packaging teams on advanced technologies (e.g., C4 bumps, micro bumps, EMIB, hybrid bonding as needed).
- Focus on design, development, and architecture, not process or materials engineering.
Required Experience:
- Experience in both silicon design (preferably mixed signal/analog) and packaging co-design.
- Background in DDR, SOC, or similar high-speed interface development.
- Hands-on expertise with bump mapping, floor planning, and packaging constraints.
- Proven ability to collaborate across silicon and packaging teams, including risk assessment and simulation.
- Familiarity with advanced packaging technologies (hybrid bonding, EMIB, etc.) is a plus but not required.
- Individual contributor or principal engineer level preferred; management experience is not required.
- Experience at leading companies in advanced packaging and PHY design (e.g., Apple, Broadcom, Qualcomm, Micron, AMD, Nvidia).
- Bachelors in electrical engineering, chemical engineering, mechanical engineering, material science or similar field (Master’s or Ph.D. preferred).
- 10+ years in silicon and packaging co-design
Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.
Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
Annual Salary Range for jobs which could be performed in the US:These jobs might be a good fit
