Technical Lead jobs in United States, California, Santa Clarita
Intel Lead Analog SerDes Architect/Design Engineer United States, California, Santa Clara
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Since pioneering the world’s first hybrid silicon laser, IPS has led the industry in scalable, high-volumemanufacturing andadvanced photonics development. Our mission: deliver next-generation bandwidth growth with smaller form factors, co-packaging, and speeds from 400G today to 1.6T+ tomorrow.
We are seeking a Lead Analog SerDes Architect / Design Engineer to join our team and shape the future of data center connectivity. In this role, you will:
- Defining circuit architecture and enabling designs meeting power, and performance for next generation optical interconnects based on system specifications.
- As part of the team developing key integrated circuit components the engineer must be able to work collaboratively leading block level development.
- Specify, architect and design low voltage and low power Mixed-Signal integrated circuits and work collaboratively with digital designers.
- Plan design work with constraints on performance, schedule and quality.
- Provide guidance to junior designers and layout engineers.
- Guidance to develop test plans for post-silicon characterization.
- Document all design work with review materials and detailed design descriptions.
Minimum QualificationsThe ideal candidate should have a minimum of MS in Electrical Engineering with 8+ years of experience in high-speed serial links and deep knowledge of analog CMOS/BiCMOS designs in deep sub-micron process technologies.• Hands-on circuit design experience of SerDes blocks like Equalizers, PLL, Phase-Interpolators, CDR, etc. for 28Gbps+ data rates.
• Experience with design of inductors, transmission line, Trans-Impedance Amplifiers (TIA) and modulator drivers.
• Experience with design of precision analog circuits like ADC/DACs.
• Experience with designing PAM4/NRZ links.
• Experience with Mixed signal design flow
• Experience with full-chip designs, ESDs and verification flows.
Preferred Qualifications
• Familiarity with Optical communications.
• Experience with 400G/800G/1.6T optical links.
• Experience with package/test setup design.
Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.
Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
Annual Salary Range for jobs which could be performed in the US: 214,730.00 USD - 303,140.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.These jobs might be a good fit
Intel Technical SoC Director United States, California, Santa Clara
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About the CTO AI Group
Intel’s CTO AI Group is at the forefront of Intel’s AI strategy. We shapethe strategy, systems, software, and silicon to move AI from potential to performance. Our team reaches across the company to drive AI forward – joining an agile, innovation-first culture with Intel’s massive scale to deliver leading-edgebreakthroughs andsolve real-world AI challenges.not just advancing AI —engineering it.
and drive cross-functionalteams. This role spans logic design, verification,and physical design, contributingthe development of IPs, sub-systems,SoCs. The ideal candidate will be passionate about engineering excellence, team development, and delivering high-quality silicon solutions.
Key Responsibilities:
Leadership & Management:
SoCengineeringdesignteams across multiple silicon design domains.
Track and reportdevelopment schedule,plans,progressand issues.
Foster a culture of accountability, continuous improvement, and highproductivity.
Design Oversight & Quality Assurance:
Conduct design reviews to ensure alignment withperformance and powertargets, in addition toSoC guidelines.
Review design health metrics and highlight potentialissues.Work with theappropriate leadertofix and follow-up on the proper design changes.
Oversee verification testplan andresultsto ensure proper planning and progress.
physical designprogress and results, especiallyon the timingside.
Drive corrective actions and ensure adherence to silicon quality standards.
with third party IP providers to ensuretheir IP deliveries match ourstandardand schedules.
Improvement:
Continuously enhance silicon development processes and architecture definitions.
Collaborate across IP and SoC teams to ensure cohesive and efficient design execution.
Additional Skills:
Excellent leadership, communication, and organizational skills.
Ability to drive cross-functional collaboration and strategic execution.
Qualifications:
BS in Electrical Engineering or Computer Science or related field with 10+ years of experience
8+ years of experience in leading silicon design teams across multiple functional areas.
Strong understanding of silicon development lifecycle and quality standards.
Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.
offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
Annual Salary Range for jobs which could be performed in the US:
$204,500.00-$288,710.00This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
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Intel DV Lead United States, California, Santa Clara
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About the CTO AI GroupOverview:Key Responsibilities:
- Verification Strategy: Devise a sound verification strategy for verifying key IP part of AI SoCs
- Verification Plan Definition: Create a solid verification plan that is not only comprehensive but also efficient.
- IP DV Development: Build scalable and re-usable UVM environments around the IPs. Create scripts to control regressions and other aspects of the function.
- Cross-Functional Collaboration: Work closely with the architecture and design teams to ensure the IPs architecture and implementation are conducive to a comprehensive and efficient verification effort. Providing feedback for this purpose will be essential to the role. Support the silicon validation effort related to the related IPs.
- Team Leadership and management: Build, mentor, and scale a small but high-performing DV team. The DV lead will also be expected to manage his team's schedules, reviews, and DV regressions, in addition to regularly presenting clear status reports to the leadership team.
Minimum Qualifications:
MS in Computer Science or Computer Engineering or related field with 8+ years of experience
8+ years of experience in verification with 1+ years of experience in AI SoCs
Scripting experience is required (Python, C or others)
Preferred Qualifications
Deep understanding of the SoC implementation flows
Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.
Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
Annual Salary Range for jobs which could be performed in the US:
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
These jobs might be a good fit
JPMorgan Branch Operations Lead - St Hope Ave Santa Barbara CA United States, California, Santa Barbara
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A typical day consists of assisting customers and performing transactions. You will also look for opportunities to make customers lives easier by setting up self-service options and building relationships. Throughout the week, you will schedule time to review branch operations and share updated policy and procedures with branch employees. This results in the business is adhering to control expectations.
- Works with the Branch Manager to set the tone of the branch environment to provide an exceptional customer experience and a dynamic and engaging culture
- Engages clients as they enter the branch by welcoming them and making customers feel appreciated, performing transactions, managing lobby traffic, checking clients into the waiting queue and scheduling/canceling client meetings
- Performs branch operations which may include managing cash devices such as the cash vault, ATM, or others while adhering to all bank policies and procedures
- Introduces customers to the branch team who will build relationships and assist with specialized financial needs
- Makes customers’ lives easier by sharing and setting up self-service options to access their accounts 24 hours a day/ 7 days a week
- Supports the Branch Manager with all aspects of branch operations, including loss control, compliance, and audit standards
- High school degree, GED, or foreign equivalent
- Detail-oriented, organized, and have the ability to multi-task with a dedication to follow policies, procedures, and regulatory banking requirements
- Availability to work Branch hours including weekends and some evenings
- Demonstrated ability to make connections, engage, and educate customers and refer to colleagues as appropriate
- Strong desire and ability to influence, educate, and connect team, partners, and customers to technology
- Demonstrated leadership abilities and proficiency in operations and transaction accuracy while working well in a team environment
- Some College level or military equivalent or 2+ years of branch banking experience
- Successful completion of the Branch Operations Lead training program is a pre-requisite to be considered active in Branch Operations Lead role
FEDERAL DEPOSIT INSURANCE ACT:
These jobs might be a good fit
Dell Technical Staff-Network Architect United States, California, Santa Clara
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shape ground-breaking products, material and processes. It’s a fascinating field of work. We’re involved in
assessing the competition, developing technology and product strategies and generating intellectual
property. We lead technology investigations, analyze industry capabilities and recommend potential
acquisitions or vendor partner opportunities. Our insights influence product architecture and definitions.
Drive Network and Fabric design based on customer requirements and required infrastructure. Address
InfiniBand, Ethernet, Accelerated Fabric Link (AFL) and other Fabric topologies that scale based on
datacenter requirements. Define Network topologies that are optimized for Training and Inferencing.
•Lead the development of end-to-end AI network architecture including Graphics Processing
Unit (GPU)-GPU, server-storage, in-rack cabling and optical design at the datacenter level
• Optimize the network topology and configuration to maximize performance of AI clusters
• Work closely with key external partners to create differentiated solutions
• Develop networking software, solutions and architecture to integrate with AI frameworks
and applications
• Expert understanding of key networking technologies to include switches, network-interface
cards (NIC), Data Processing Units (DPU) and AI Fabrics
• Experience in AI framework integration (e.g., TensorFlow, PyTorch, Kubernetes for ML
workloads)
• Experience with data center network design and optical distribution
• Knowledge of networking protocol industry standards
• Customer and partner project/program leadership experience; must have ability to
understand and assess customer requirements, develop technical solutions based on
customers geographical area, negotiate conflicting interests and prioritize deliverables to
achieve the best possible outcome for all stakeholders; need to be able to travel 20%-30%
Desirable Requirements
• 15+ years industry experience with bachelor’s degree or equivalent skill
• Possess relationships with key suppliers of networking products
$216,750 - $323,400
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Dell Technical Staff-Hardware Architect United States, California, Santa Clara
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You will:
Drive hardware design based on customer requirements and required infrastructure. Address liquid cooling solutions and other mechanical engineering aspects that scale based on datacenter requirements. Define hardware topologies that are optimized for efficiency and performance.
Lead the development of end-to-end datacenter hardware architecture including CDU, cold-plates, manifold, rack, and skid at the datacenter level.
Optimize the hardware configuration to maximize performance and efficiency of datacenter components.
Work closely with key external partners to create differentiated solutions.
Develop hardware solutions and architecture to integrate with datacenter frameworks and applications.
Essential Requirements
10+ years applicable industry experience or equivalent skill; must include expert understanding of key mechanical engineering technologies related to datacenter components such as CDU, cold-plates, manifold, rack, and skid.
Proficiency using tools like Creo
Experience with datacenter hardware design and liquid cooling solutions.
Knowledge of mechanical engineering industry standards.
Customer and partner project/program leadership experience; must have the ability to understand and assess customer requirements, develop technical solutions based on customers' geographical area, negotiate conflicting interests, and prioritize deliverables to achieve the best possible outcome for all stakeholders; need to be able to travel 20%-30%.
Desirable Requirements
Masters, PhD or Bachelor’s degree or equivalent experience
Possess relationships with key suppliers ofdatacenter products & components.
$200,000.00 - $295,000.00
These jobs might be a good fit
Dell Technical Staff-Network Architect United States, California, Santa Clara
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on our
You will:
Drive Network and Fabric design based on customer requirements and required infrastructure. Address InfiniBand, Ethernet, Accelerated Fabric Link (AFL) and other Fabric topologies that scale based on datacenter requirements. Define Network topologies that are optimized for Training and Inferencing.
- Lead the development of end-to-end AI network architecture including Graphics Processing Unit (GPU)-GPU, server-storage, in-rack cabling and optical design at the datacenter level
- Optimize the network topology and configuration to maximize performance of AI clusters
- Work closely with key external partners to create differentiated solutions
- Develop networking software, solutions and architecture to integrate with AI frameworks and applications
Essential Requirements
- Expert understanding of key networking technologies to include switches,network-interface cards (NIC), Data Processing Units (DPU) and AI Fabrics
- Experience in AI framework integration (e.g., TensorFlow, PyTorch, Kubernetes for ML workloads)
- Experience with data center network design and optical distribution
- Knowledge of networking protocol industry standards
- Customer and partner project/program leadership experience; must have ability to understand and assess customer requirements, develop technical solutions based on customers geographical area, negotiate conflicting interests and prioritize deliverables to achieve the best possible outcome for all stakeholders; need to be able to travel 20%-30%
Desirable Requirements
- 15+ years industry experience with bachelor’s degree or equivalent skill
- Possess relationships with key suppliers of networking products
$216,750 - $323,400
These jobs might be a good fit
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Since pioneering the world’s first hybrid silicon laser, IPS has led the industry in scalable, high-volumemanufacturing andadvanced photonics development. Our mission: deliver next-generation bandwidth growth with smaller form factors, co-packaging, and speeds from 400G today to 1.6T+ tomorrow.
We are seeking a Lead Analog SerDes Architect / Design Engineer to join our team and shape the future of data center connectivity. In this role, you will:
- Defining circuit architecture and enabling designs meeting power, and performance for next generation optical interconnects based on system specifications.
- As part of the team developing key integrated circuit components the engineer must be able to work collaboratively leading block level development.
- Specify, architect and design low voltage and low power Mixed-Signal integrated circuits and work collaboratively with digital designers.
- Plan design work with constraints on performance, schedule and quality.
- Provide guidance to junior designers and layout engineers.
- Guidance to develop test plans for post-silicon characterization.
- Document all design work with review materials and detailed design descriptions.
Minimum QualificationsThe ideal candidate should have a minimum of MS in Electrical Engineering with 8+ years of experience in high-speed serial links and deep knowledge of analog CMOS/BiCMOS designs in deep sub-micron process technologies.• Hands-on circuit design experience of SerDes blocks like Equalizers, PLL, Phase-Interpolators, CDR, etc. for 28Gbps+ data rates.
• Experience with design of inductors, transmission line, Trans-Impedance Amplifiers (TIA) and modulator drivers.
• Experience with design of precision analog circuits like ADC/DACs.
• Experience with designing PAM4/NRZ links.
• Experience with Mixed signal design flow
• Experience with full-chip designs, ESDs and verification flows.
Preferred Qualifications
• Familiarity with Optical communications.
• Experience with 400G/800G/1.6T optical links.
• Experience with package/test setup design.
Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.
Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
Annual Salary Range for jobs which could be performed in the US: 214,730.00 USD - 303,140.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.These jobs might be a good fit
