Help solving one of the PC bottlenecks – memory throughput by:

Building behavioral analog model of DDR subsystem. Building algorithmic model that mimics the training portion of DDR PHY. Writing tool that combines the above. Interface the tool with the operational PC environment. Using the developed tool to verify system operation before Si in house stage, algorithm optimization, debug issues after Si arrival. Working with many lateral teams to gather the required data. Work outcome should influence and increase memory BW on every PC.

Experience in writing simulations using either Matlab, Python or equivalent. Analog orientation: understanding analog world of high-speed interface. Experience in one or more of the following:

High speed analog design / debug / integration

High speed board design / signal integrity.

Modem design / integration / debug

Analog aspects of DDR memory interface

Programming in C