ICG is developing cutting-edge Imaging solutions from the IP level into full SOC solutions, based on computer vision, and AI that will serve various corresponding markets as well as enrich vision use cases and future user experiences for the Imaging world.

Working on a complex SoC system that includes AI Logic, Automotive ASILA-D and Camera Pipe

you are going to be part of the Front to Back End team which is responsible for:

• Develop cutting edge synthesis and Place && Route methodologies in advanced process node for external and internal foundries
• Define all synthesis design constraint
• Working closely with the Design Team and the design automation team
• IP-Level and Full Chip SDC timing development and timing check
• STA: work with FE and floor planner to manage block and top level constraints and 1st level of timing analysis
• Static Timing Analysis and debug
• RTL quality checks i.e. check design, check timing etc
• Physical synthesis Place && Route
• Floor planning
• Logical Equivalence (LEC, Formality)
• BE support

What Are We Looking For?

• Bachelor's degree or above in Electronics Engineers or Computer Engineering or equivalent
• Minimum 2 years of experience in synthesis Flow: Design Compiler or Genus
• Experience with Timing constraints and Static Timing Analyzer : Prime Time or Tempus
• Design automation skill and proficiency in scripting languages
• Advantage: Formality/LEC, Back End Flows , Strong Hardware engineering skills