As part of the team, you will be part of the global effort to:

• Define, design, verify, and document RTL development in Verilog/System Verilog of complex worldwide strategic IPs
• Interact closely with architecture teams and all SOC teams in Western digital
• Work and develop under world-class ASIC methodology development stages
• Significant contribution to design and verification and methodology on making complex IPs and flows
• Become a significant person on a vast growing team

Your responsibilities will be to:

• Review the design specifications and noting likely points of failure
• Design verification strategy and methodology based on a design specification
• Planning and execution the method of sequence for testing operations
• Meets time and quality goals with little direction and supervision

• Previous experience of at least 7 years as a Verification Engineer
• BSc in Electrical Engineering
• Detailed knowledge of UVM based verification methodology
• Excellent analytical and debugging skills
• A good eye for details
• Advanced verbal and written communication skills
• Collaborates to develop self and others within the group