You will create emulation/Field Programmable Gate Array (FPGA) models from a Register Transfer Level (RTL) design using emulation/FPGA synthesis, partitioning and routing tools.

You will define and document RTL changes required for emulation/FPGA. Develops hardware and software collaterals and integrates it with the emulation/FPGA model.

You will test and debug the emulation/FPGA model and collaterals.

You will define and develop new capabilities & HW/SW tools to enable acceleration of RTL and improve emulation/FPGA model usability for preSilicon and postSilicon functional validation as well as SW development/validation.

You will develop improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform.

You will interface with and provides guidance to presilicon Validation teams for optimizing preSi validation environments, test suites and methodologies for emulation efficiency.

You will develop and apply automation aids, flows and scripts in support of emulation ease of use and improvement of equipment utilization.

Qualifications

• Electrical Engineer with 5 years of Verilog coding and synthesis experience.
• On hands experience leading enablement and bring-up of systems.

Preferred Qualifications:

• PCIe and Ethernet deep debug know-how.
• Both Emulator and FPGA know-how.
• Large SOC experience.