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Coherent Interconnect Design Engineer RTL High Tech Jobs

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Google

Coherent Interconnect Design Engineer RTL

Israel, Tel Aviv
Details

Note: By applying to this position you will have an opportunity to share your preferred working location from the following: .


Qualifications

Minimum qualifications:

  • Bachelor's degree in Computer Science or Electrical Engineering or equivalent practical experience.
  • Experience with design, implementation, and functional verification.
  • Experience with power efficiency and performance estimation automation.
  • Experience with multiple full SoC design cycles.

Preferred qualifications:

  • Master's or PhD degree in Computer Science or Electrical Engineering or equivalent practical experience.
  • Experience in ARM CPU coherent interconnect development.
  • Experience implementing engineering best practices (e.g., design reviews, code reviews, testing).
About the job

As a Coherent Interconnect Design Engineer, you will be responsible for microarchitecture, RTL design and implementation of cache coherent interconnect technology as part of Google’s data center SoC products. You will work alongside other RTL design, physical design and verification engineers and with direction from CPU and SoC architects and design leads during the microarchitecture, design, verification, and bringup phases of product development.

Responsibilities
  • Manage the microarchitecture, design, and implementation of high-bandwidth, multi-core cache coherent interconnect RTL for SoCs that power Google's computing infrastructure.
  • Focus on coherency function as well as performance from the concept/planning stage through execution and closure.
  • Work with architecture, design, verification, and bringup teams to ensure product success.
  • Work jointly with CPU design SoC integration teams, ensuring successful integration of the CC interconnect into SoC.
  • Translate microarchitecture specifications to the physical design and power aware implementation in SystemVerilog.
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