Highly visible and multi-disciplinary role driving SoC power simulation and optimization for Intel leading products.

The role requires advanced understanding of SoC behavior and power modeling, testing and BE&FE design optimizations driving power reduction and optimization thru the different phases of Product development stages (from pathfinding to Silicon)

The role requires programing and SW development skills to take part in power modeling tools development.

It includes the following:

Understanding overall product targets and directions

Development of new power modeling tools and enhancing power modeling capabilities

Integration of IPs to the SoC level and define IP power targets and focus areas

Qualifications

• B.Sc. in Computer Engineering, or Electrical Engineering.
• Minimum 2 years of Circuit, logic design or integration experience
• Programing and/or SW development background (python programming skills is a benefit)
• Experience in power modeling methodologies and low power optimization is an advantage
• Experience in BE Design (FE is benefit)
• Advanced understanding of power considerations at architectural, block and circuit levels is benefit
• In this highly visible role - strong communication skills are a pre-requisite as the candidate will interface with many of different groups and organizations