Gpu Performance Architect Memory System jobs at Samsung in United States, Austin

Role and Responsibilities

You will own and contribute to end-to-end GPU silicon debug and post-silicon validation across complex SoC systems through diagnostic development and automation.

• You are an innovator. You excel at bringing up and debugging GPU and SoC hardware/software systems, including Linux/Android kernel and firmware environments.

• You are a problem solver. You enjoy distilling complex problems at the root cause by using tools like Lauterbach, scan chain, and waveform analysis for issue isolation and resolution.

• You are forward-thinking. You challenge conventional methods by developing tools or scripts to automate GPU functional validation and SoC-level system tests—improving coverage, efficiency, and speed.

• You take ownership in delivering high quality results. You proactively analyze SoC emulation scenarios to identify and resolve functional or performance challenges.

• You are a team player. You proactively build cross-functional collaboration with design, verification, and software teams to drive resolution and continuous improvements for next-gen GPU designs.

• You are a lifelong learner. You stay current with emerging technologies and continuously sharpen your skills through learning and experimentation.

Skills and Qualifications

• 5+ years of experience with a Bachelor's Degree in Computer Engineering or comparable field, or 3+ years of experience with a Master’s Degree, or 1+ year of experience with a Ph.D.

• 5+ years of experience inpre-silicon/post-silicondebug validation

• GPU architectural knowledge and development experience

• Experience with GPU and Microprocessor Debug using Logic Analyzer, Scopes, and other test equipment

• Familiarity with GPU APIs (OGL, OCL, Vulkan) and GPU software stacks

• Experience with C/C++/Object Oriented programming, Python, Shell Scripting

• Availability to work on-site 5 days a week

• Preferred experience:

• Hands-on experience with System and board level bring up

• Hands-on experience using debugger such as Lauterbach to debug software/SOC

• Familiarity with performance and power measurement techniques

• Familiarity with scanchain, array dump, HW debug techniques

• Familiarity with emulator signal extraction from waveform techniques

• Familiarity with IPXACT design documents and parser software development

• Familiarity with GPU and Microprocessor Product and Test engineering

• Programming skills: Linux, Android Kernel, BIOS, Firmware

• Experience with Verilog, UVM

• Experience with driving debug effort across design, verification and software organization

Total Rewards

This is an exempt position, which is not eligible for overtime pay under the Fair Labor Standards Act (FLSA).

U.S. Export Control

This position requires the ability to access information subject to U.S. export control restrictions. Applicants must have the ability to access export-controlled information or be eligible to receive a government authorization to access export-controlled information.

Role and Responsibilities

As a Lead Memory Controller Architect/uArch, you will drive the design and development of advanced memory controller for cutting-edge technologies such as LPDDR5, LPDDR6, PIM (Processing in Memory), and beyond (DDR5, GDDR7, HBM4).

As a key player in this critical position, you will have end-to-end ownership for memory-controller architecture, including microarchitecture, RTL design, and performance/power optimization. You will work closely with cross-functional teams, such as system architects, verification, performance/power, and design implementation, to bring innovative ideas to life and develop cutting-edge memory technologies for Samsung's next-generation products. This role offers a unique opportunity to be at the forefront of the entire technology development cycle, allowing you to expand your expertise in memory controllers and push the boundaries of what is possible, shaping the future of memory technology.

• You possess a strong engineering foundation and extensive experience in architecture, enabling you to lead the development of custom memory controllers, including micro-architecture, RTL design, debugging, and timing closure.
• You have a passion for microarchitecture development, excel at driving the creation of high-quality RTL from initial architectural exploration to final delivery, meeting performance, power, and area (PPA) targets while adhering to project schedules.
• You ensure design excellence, utilizing various tools and methodologies, including LINT, CDC, ECO flows, and power analysis (PowerArtist), to validate design quality and identify areas for improvement.
• You collaborate with cross-functional teams, you foster strong partnerships with stakeholders to guarantee design functionality, achieve PPA objectives, and overcome implementation challenges in a dynamic environment with shifting priorities.
• You take pride in your deliverables, assuming ownership of your work by adhering to JEDEC standards, collaborating with SOC IP delivery teams, performing thorough sanity checks, supporting timing debug and closure, and applying your knowledge of DDR PHY to drive successful outcomes.

Skills and Qualifications

• 20+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 18+ years of experience with a Master’s Degree, or 16+ years of experience with a PhD
• Proven experience in memory controller micro-architecture and RTL design, owning all sub-blocks of custom memory controller designs.
• Deep expertise in multiple memory technologies, such as LPDDR4/5/6, PIM, DDR, GDDR, and HBM.
• Strong knowledge of JEDEC memory standards and working knowledge of DDR PHY.
• Demonstrated success in driving architecture through RTL design for high-performance digital systems.
• Strong expertise in Verilog and ASIC design flow, including RTL design, verification, synthesis, timing analysis, and ECO.
• Proficiency in scripting languages (Perl, Python) to support design and automation.
• Strong communication and collaboration skills; able to navigate ambiguity in a fast-paced, global team environment.
• Familiarity with interface protocols (AMBA, AXI, ACE) is desired.
• Knowledge of AES, ECC, and RAS features is preferred.
• Self-driven, curious, and passionate about logic design and innovation.

With architecture scalability at the frontier of our design focus, our performance- and power-optimized IP solution gets integrated into complex semiconductor products, aiming to reach multiple market segments.

Being part of a new team of talented individuals with vastly diverse backgrounds and skill sets at a well-established global company means you have limitless room to explore, innovate, and expand role responsibilities to build technical expertise. With a big charter ahead, we get to do challenging work and solve unique problems in a highly collaborative and supportive environment. You will always be learning while helping us shape the team’s culture.

U.S. Export Control

This position requires the ability to access information subject to U.S. export control restrictions. Applicants must have the ability to access export-controlled information or be eligible to receive a government authorization to access export-controlled information.

Role and Responsibilities

As a Sr. Memory Controller Micro-Architect, you will lead the design and development of advanced memory controller for cutting-edge technologies such as LPDDR5, LPDDR6, PIM (Processing in Memory), and beyond (DDR5, GDDR7, HBM4).

In this high-impact role, you will have ownership and influence entire memory-controller related micro-architecture, RTL design, and performance/power optimization.As part of a true global task force, you will collaborate closely with system architects, verification, performance/power, design implementation, and other teams to transform bold ideas into next-generation memory technologies for Samsung. You are empowered to deepen your expertise in memory controller by being at the forefront of a full technology development cycle and redefining what’s possible.

• You are a domain expert in one or more technical areas with solid engineer foundation and RTL design experience. You will drive the micro-architecture, RTL design, debug, and timing closure for custom memory controllers.
• You are passionate about handling microarchitecture development and specification – from early high-level architectural exploration through micro architectural research and delivering high quality RTL on schedule to meet performance, power, an area (PPA) goals.
• You ensure design quality through LINT, CDC, ECO flows, and power analysis (PowerArtist).
• You have a collaborative mindset and build strong cross-functional partnerships with various stakeholders to ensure design functionality, achieve PPA goals, and resolve implementation challenges with evolving priorities in a fast-paced environment.
• You take ownership in your deliverables by adhering to JEDEC standards and timing parameters, collaborating with SOC IP delivery with all sanity checks, supporting timing debug and closure, and applying knowledge of DDR PHY.

Skills and Qualifications

• 20+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 18+ years of experience with a Master’s Degree, or 16+ years of experience with a PhD
• Proven experience in memory controller micro-architecture and RTL design, owning all sub-blocks of custom memory controller designs.
• Deep expertise in multiple memory technologies, such as LPDDR4/5/6, PIM, DDR, GDDR, and HBM.
• Strong knowledge of JEDEC memory standards and working knowledge of DDR PHY.
• Demonstrated success in driving architecture through RTL design for high-performance digital systems.
• Strong expertise in Verilog and ASIC design flow, including RTL design, verification, synthesis, timing analysis, and ECO.
• Proficiency in scripting languages (Perl, Python) to support design and automation.
• Strong communication and collaboration skills; able to navigate ambiguity in a fast-paced, global team environment.
• Familiarity with interface protocols (AMBA, AXI, ACE) is desired.
• Knowledge of AES, ECC, and RAS features is preferred.
• Self-driven, curious, and passionate about logic design and innovation.

With architecture scalability at the frontier of our design focus, our performance- and power-optimized IP solution gets integrated into complex semiconductor products, aiming to reach multiple market segments.

Being part of a new team of talented individuals with vastly diverse backgrounds and skill sets at a well-established global company means you have limitless room to explore, innovate, and expand role responsibilities to build technical expertise. With a big charter ahead, we get to do challenging work and solve unique problems in a highly collaborative and supportive environment. You will always be learning while helping us shape the team’s culture.

U.S. Export Control

This position requires the ability to access information subject to U.S. export control restrictions. Applicants must have the ability to access export-controlled information or be eligible to receive a government authorization to access export-controlled information.

Role and Responsibilities

As a GPU Performance Architect (Memory System), you will work as part of the GPU Architecture team where you will drive the modeling and analysis of memory-system features for a highly efficient mobile GPU. You have a curious mindset that thrives on navigating the unknown through innovation and continuous learning. You will contribute towards current and future plans strategy.

We believe in connecting your area of expertise with the right level and functional discipline that can empower you to grow. You will have the unique opportunity to explore and contribute to the graphics pipeline, while broadening your knowledge in different aspects of GPU development.

• You work closely with the architecture, SW, and design teams to understand the architecture and micro-architecture of the GPU memory system including cache hierarchy, bus unit, interfaces with the GPU core and rest of the SoC.
• You develop complex GPU performance models to help define micro-architectural features and implementation optimizations of next-generation GPUs, in areas of memory system.
• You develop tools and methodology to correlate and validate performance models, triage and fix performance issues, and identify bottlenecks and propose solutions to improve GPU performance.
• You drive high-level performance analysis on complex workloads, with the goal to optimize the GPU with rest of the Memory System IP (Interconnect, Last-level Cache, Memory Controller).

Skills and Qualifications

• 10+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 8+ years of experience with a Master’s Degree, or 6+ years of experience with a PhD
• 5+ years of experience in architectural modeling and performance analysis, either with analytical models or cycle-accurate simulators
• Experience with CPU, GPU, or Memory systems microarchitecture
• Good programming and/or scripting skills (Python is a plus)
• Good understanding of power/performance trade-offs
• Good understanding of VLSI concepts, HW design
• Good written and verbal communication skills

• Performance modeling or workload analysis experience, in areas of memory subsystems
• Knowledge of Core Pipelines (CPU, GPU or Accelerators)
• Directly related experience with correlation of RTL with performance model
• Experience in integrating internal/external IP models on a full system-level framework.

U.S. Export Control

This position requires the ability to access information subject to U.S. export control restrictions. Applicants must have the ability to access export-controlled information or be eligible to receive a government authorization to access export-controlled information.

Role and Responsibilities

As a Sr. Memory ControllerMicro-Architect/LogicDesigner, you will contribute to the micro-architecture development and logic design of our advanced custom memory controller for LPDDR5/6. This is a senior level role where you will interact with the system architects, verification, performance/power and design implementation teams. You will be own and drive the critical memory controller related RTL design, performance and power optimization, and also work on logic debug and timing closure of the design. Solid engineer foundation and RTL design experience are desired for success.

• You drive the timely development and debug of new features on timely development of custom memory controller.
• You work on SOC IP delivery with all sanity checks.
• You work on timing debug and closure.
• You work on LINT, CDC flows and analysis.
• You work on power artist flow and power analysis.
• You have experience working on ECO flows.
• You collaborate with the verification team to verify the functionality and correctness of the design.
• You communicate with implementation to achieve your timing and area.
• You produce high quality RTL on schedule meeting PPA goals
• You engage with performance and power team on achieving performance and power goals.
• You partner with the physical design and CAD team to resolve implementation level details.

Skills and Qualifications

• 15+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 13+ years of experience with a Master’s Degree, or 11+ years of experience with a PhD
• Strong background owning and driving the RTL design of various sub-blocks of custom memory controller designs
• Experience working with memory controller u-architecture on different memory technologies like LPDDR5/6, GDDR, PIM, HBM
• Demonstrated experience of successful Architectural through RTL design on high performance digital designs
• Verilog expertise is required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, timing analysis & ECO
• Knowledge of JEDEC memory standards preferred
• Understanding of interface protocols such as AMBA, AXI, ACE is desired
• Knowledge of AES, ECC, RAS features preferred
• Strong communication and interpersonal skills are required, along with the ability to work in a dynamic, global team
• Experience with a scripting language like Perl or Python
• Energetic, curiosity, and passion in logic design

With architecture scalability at the frontier of our design focus, our performance- and power-optimized IP solution gets integrated into complex semiconductor products, aiming to reach multiple market segments.

Being part of a new team of talented individuals with vastly diverse backgrounds and skill sets at a well-established global company means you have limitless room to explore, innovate, and expand role responsibilities to build technical expertise. With a big charter ahead, we get to do challenging work and solve unique problems in a highly collaborative and supportive environment. You will always be learning while helping us shape the team’s culture.

U.S. Export Control

This position requires the ability to access information subject to U.S. export control restrictions. Applicants must have the ability to access export-controlled information or be eligible to receive a government authorization to access export-controlled information.

Role and Responsibilities

The GPU Software team is looking for experienced Graphics Engineers with expertise in Vulkan and Ray Tracing to design, develop, and optimize graphics rendering engines for our next-generation products. As a key member of our graphics team, you will be responsible for developing high-performance, power-efficient, and scalable graphics solutions that meet the demands of emerging applications, including gaming, virtual reality, and augmented reality.

You will join a team that builds a framework using Vulkan for internal tooling and advanced graphics exploration. You will leverage your knowledge and passion for graphics, rendering, performance, and video games to contribute to the development of new GPU software features. Your responsibilities will include developing and optimizing Vulkan-based graphics rendering engines, integrating Vulkan drivers with our SoC and GPU architectures, and designing and implementing real-time ray tracing algorithms and techniques.

Key responsibilities include:

• You will possess a strong knowledge of Vulkan, OpenGL, and/or DirectX.

• You will design and develop real-time ray tracing algorithms and techniques for our graphics rendering engines.

• You are skilled at software development in C/C++/Python. You will apply advanced knowledge ofLinux, and Android Operating systems for coding environment and target device development.

• You are passionate about proactively collaborating with hardware and software teams on high-impact, large-scale projects and initiatives.

• You enjoy applying best practices using git, gerrit (code reviews), continuous integration.

• You take ownership in delivering high quality outcomes, including managing debugging driver failures and performance issues using code and graphics debugging tools.

• You are organized and adept at providing high-level documentation and communications using common project management tools (JIRA, Confluence, Wiki, Chat, Email).

• You are a lifelong learner who enjoy researching new API changes and trends in graphics for future GPU enhancements.

• You bring fresh ideas to challenge past practices, approaches, and old ways of thinking to unlock new opportunities for product improvement or development flow.

Skills and Qualifications

• 5+ years of graphics software engineering experience with a Bachelor’s degree in Computer Science/Computer Engineering/relevant technical field, or 3+ years of experience with a Master’s degree, or 2+ years of experience with a PhD

• 5+ years of experience with programing skills (C, C++, Python)

• 5+ years of object-oriented and component-based design experience

• Effective problem solving and communications skills

• Experience with working directly with graphics APIs, graphics drivers or Game Engine subsystems for graphics (e.g., Vulkan, OpenGL, OpenCL, Metal, Direct X, ANGLE)

• Experience writing GLSL, HLSL shaders

• Strong understanding of graphics hardware

• Deep knowledge of graphics algorithms and rendering

• Deep knowledge of 3D math (including linear algebra)

• Android application development and debugging experience

• Graphics debugging experience using performance or frame inspection tools

• Game Engine experience: Unity, Unreal, etc.

U.S. Export Control

This position requires the ability to access information subject to U.S. export control restrictions. Applicants must have the ability to access export-controlled information or be eligible to receive a government authorization to access export-controlled information.

Role and Responsibilities

As a Senior Coherent Interconnect Micro-Architect, you will be responsible for leading the micro-architecture development of custom coherent interconnect IP and/or last level cache blocks. In this role you will be interacting with the system architects, verification, performance/power and design implementation teams. You will be owning and driving the critical coherent interconnect related RTL design, performance and power optimization and also work on logic debug and timing closure of the design. Solid engineer foundation and RTL design experience are desired for success.

• You drive the timely development of custom coherent interconnect IP and/or last level cache [LLC] blocks.
• You engage with the architects and help define next-generation Samsung coherent interconnects and LLC.
• You perform microarchitecture development and specification - from early high-level architectural exploration through micro architectural research and arriving at a detailed specification
• You work with the verification team to verify the functionality and correctness of the design.
• You collaborate with implementation to achieve your timing and area.
• You produce quality RTL on schedule meeting PPA goals
• You engage with performance and power team on achieving performance and power goals.
• You partner with the physical design and CAD team to resolve implementation level details.
• You Help mentor junior engineers in the team.

Skills and Qualifications

• 15+ years of experience with a Bachelor’s degree in Computer Science/Computer Engineering/relevant technical field, or 13+ years of experience with a Master’s degree, or 11+ years of experience with a PhD
• Strong background owning and driving the RTL design of various sub-blocks of the coherent interconnect or memory controller or LLC for the high performance digital designs
• Demonstrated experience of successful Architectural through RTL design experience on high performance digital designs
• Verilog expertise is required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.
• Knowledge of system caches and directory snoop filter protocols.
• Familiarity with different on-chip network topologies: mesh, ring, crossbar.
• Experience in leading and mentoring a team of engineers.
• Knowledge of in Arm AMBA5 CHI, AMBA4 ACE or AXI coherent interconnect and bus protocols
• Knowledge of memory subsystem design including coherent cache design.
• Strong communication and interpersonal skills are required along with the ability to work in a dynamic, global team.

• Knowledge of Verilog/VHDL, scripting, STA, DFT, ECO flows.
• Proficient in AMBA, ACE, AXI, CHI protocols.
• Knowledge of memory controller and either coherent interconnect or cache design.
• Knowledge of memory subsystem, coherency, directory snoop filter protocols.
• Familiarity with different on-chip network topologies: mesh, ring, crossbar.
• Experience with a scripting language like Perl or Python.
• Energetic, curiosity, and passion in logic design.
• Good written and verbal communication skills.
• Efficient digital design techniques.

With architecture scalability at the frontier of our design focus, our performance- and power-optimized IP solution gets integrated into complex semiconductor products, aiming to reach multiple market segments.

Being part of a new team of talented individuals with vastly diverse backgrounds and skill sets at a well-established global company means you have limitless room to explore, innovate, and expand role responsibilities to build technical expertise. With a big charter ahead, we get to do challenging work and solve unique problems in a highly collaborative and supportive environment. You will always be learning while helping us shape the team’s culture.

U.S. Export Control

This position requires the ability to access information subject to U.S. export control restrictions. Applicants must have the ability to access export-controlled information or be eligible to receive a government authorization to access export-controlled information.